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? symbios ? SYM53C710 scsi i/o processor order number s14032 technical manual march 2000 version 3.1
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic officer is prohibited. document db14-000117-00, fifth edition (march 2000) this document describes the lsi logic corporation?s symbios ? SYM53C710 scsi i/o processor and will remain the official reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1993?2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, symbios, tolerant, and scripts are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
preface iii preface this book is the primary reference and technical manual for the SYM53C710 scsi i/o processor. it contains a complete functional description for the product and includes complete physical and electrical specifications. audience this manual assumes some prior knowledge of current and proposed scsi and pci standards. organization this document has the following chapters and appendixes: ? chapter 1, general description , includes general information about the SYM53C710. ? chapter 2, functional description , describes the main functional areas of the chip in more detail, including interfaces to the scsi bus and external memory. ? chapter 3, signal descriptions , contains pin diagrams and signal descriptions. ? chapter 4, registers , describes each bit in the operating registers, and is organized by register address. ? chapter 5, instruction set of the i/o processor , defines the scsi scripts instructions supported by the SYM53C710. ? chapter 6, electrical specifications , contains the electrical characteristics and ac timing diagrams. ? appendix a, register summary , is a register summary.
iv preface ? appendix b, register and bit differences between the SYM53C710 and sym53c700 , explains the differences between the SYM53C710 and sym53c700. ? appendix c, mechanical drawing , is a mechanical drawing. ? appendix d, setting data transfer rates , explains how to get the proper data transfer speed on the scsi bus. related publications for background please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-1994 (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface scsi electronic bulletin board (719) 533-7950
preface v lsi logic internet anonymous ftp site ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi lsi logic world wide web home page www.lsilogic.com pci special interest group 2575 n.e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the prefix ?0x? ?for example, 0x32cf. binary numbers are indicated by the prefix ?0b? ?for example, 0b0011.0010.1100.1111. revision record revision date remarks 0.1 2/90 draft. 0.2 4/90 draft. 0.3 5/90 draft. 0.99 8/90 draft. 1.0 9/90 preliminary version. 2.0 9/91 complete rewrite. 2.1 6/92 move chapter 6, electrical specifications, to separate manual. 3.0 11/93 chapter 6, electrical specifications, incorporated back into data manual; misaligned transfers section modified; updates to chapter 4; appendix d added with appropriate sens. 3.1 3/00 miscellaneous cosmetic/format changes from symbios to lsi logic.
vi preface
contents vii contents chapter 1 general description 1.1 SYM53C710 features summary 1-2 1.1.1 performance 1-2 1.1.2 integration 1-3 1.1.3 ease of use 1-3 1.1.4 flexibility 1-3 1.1.5 reliability 1-4 1.1.6 testability 1-4 chapter 2 functional description 2.1 scsi core 2-1 2.1.1 dma core 2-2 2.2 scripts processor 2-2 2.2.1 loopback mode 2-3 2.2.2 parity options 2-3 2.3 dma fifo 2-7 2.3.1 interrupted transfer cleanup 2-7 2.4 host interface 2-9 2.4.1 big/little endian support 2-9 2.4.2 big endian mode 2-10 2.4.3 little endian mode 2-10 2.4.4 misaligned transfers 2-11 2.4.5 cache line bursting 2-11 2.4.6 cache line burst with start of transfer misaligned 2-12 2.4.7 cache line burst with end of transfer misaligned 2-13 2.4.8 programmable bursting 2-15
viii contents 2.4.9 programmable burst with start of transfer misaligned 2-15 2.4.10 programmable burst with end of transfer misaligned 2-17 2.4.11 host bus retry 2-18 2.5 bidirectional sterm/_ta/ 2-19 2.6 interrupts 2-21 2.6.1 polling vs. hardware interrupts 2-21 2.6.2 registers 2-21 2.6.3 fatal vs. nonfatal interrupts 2-22 2.6.4 masking 2-23 2.6.5 stacked interrupts 2-24 2.6.6 halting in an orderly fashion 2-25 2.6.7 sample interrupt service routine 2-25 2.7 scsi bus interface 2-26 2.7.1 terminator networks 2-27 2.7.2 select/reselect during selection/reselection 2-27 2.7.3 synchronous operation 2-28 chapter 3 signal descriptions chapter 4 registers 4.1 register descriptions 4-1 chapter 5 instruction set of the i/o processor 5.1 getting started 5-3 5.2 i/o instructions 5-10 5.3 read/write instructions 5-19 5.3.1 read-modify-write cycles 5-21 5.3.2 move to/from sfbr cycles 5-21 5.4 transfer control instructions 5-22 5.5 memory move instructions 5-29 5.5.1 read/write system memory from scripts 5-31
contents ix chapter 6 electrical specifications 6.1 dc characteristics 6-1 6.2 symbios tolerant specifications 6-6 6.3 ac specifications 6-10 6.4 bus mode 1 slave cycle 6-14 6.4.1 bus mode 1 slave read sequence 6-14 6.4.2 bus mode 1 slave write sequence 6-18 6.5 host bus arbitration 6-21 6.5.1 bus arbitration sequence 6-21 6.6 bus mode 1 fast arbitration 6-25 6.6.1 fast arbitration sequence 6-25 6.7 bus mode 1 bus master cycle 6-28 6.7.1 bus mode 1 bus master read sequence 6-28 6.7.2 bus mode 1 bus master write sequence 6-33 6.8 bus mode 2 slave cycle 6-38 6.8.1 bus mode 2 slave read sequence 6-38 6.8.2 bus mode 2 slave write sequence 6-42 6.9 host bus arbitration 6-46 6.9.1 bus arbitration sequence 6-46 6.10 bus mode 2 fast arbitration 6-50 6.10.1 fast arbitration sequence 6-50 6.11 bus mode 2 bus master cycle 6-53 6.11.1 bus mode 2 bus master read sequence 6-53 6.11.2 bus mode 2 bus master write sequence 6-58 6.12 bus mode 2 mux mode operation 6-63 6.12.1 mux mode read cycle (cache line and noncache line burst) 6-63 6.12.2 mux mode write cycle (cache line and noncache line burst) 6-66 appendix a register summary appendix b register and bit differences between the SYM53C710 and sym53c700 appendix c mechanical drawing
xcontents appendix d setting data transfer rates d.1 setting the sym53c700-66 transfer rate d-1 d.2 sym53c7xx, sym53c8xx to 75lbc976/76a differential interface d-3 d.2.1 differential mode d-3 d.2.2 ti 75lbc976 architecture d-4 d.2.3 interface d-5 d.2.4 pull-up resistor value d-5 d.2.5 8-bit/16-bit scsi and the differential interface d-6 index customer feedback figures 1.1 SYM53C710 block diagram 1-5 2.1 dma fifo sections 2-7 2.2 SYM53C710 data paths 2-9 2.3 cache line bursting, start of transfer (little endian mode) 2-13 2.4 cache line bursting, end of transfer (little endian mode) 2-14 2.5 programming bursting, start of transfer (little endian mode) 2-16 2.6 programming bursting, start of transfer (little endian mode) 2-18 2.7 slack/ tied back to sterm/_ta/ (ea bit not set) 2-20 2.8 bidirectional sterm/ (ea bit set) 2-20 2.9 differential wiring diagram 2-29 2.10 alternative two termination (example 1) 2-30 2.11 alternative two termination (example 2) 2-31 3.1 SYM53C710 pin configuration 3-2 5.1 block move instruction register 5-4 5.2 i/o instruction register 5-10 5.3 read/write instruction register 5-19 5.4 transfer control instruction register 5-22 5.5 memory move instruction register 5-29 6.1 rise and fall time test conditions 6-7
contents xi 6.2 scsi input filtering 6-7 6.3 hysteresis of scsi receiver 6-8 6.4 input current as a function of input voltage 6-9 6.5 output current as a function of output voltage 6-9 6.6 clock timing 6-10 6.7 chip reset timing waveforms 6-12 6.8 irq timing waveforms 6-13 6.9 bus mode 1 slave read cycle 6-17 6.10 bus mode 1 slave write cycle 6-20 6.11 bus mode 1 host bus arbitration cycle 6-24 6.12 bus mode 1 fast arbitration 6-27 6.13 bus mode 1 bus master read cycle (noncache line burst) 6-31 6.14 bus mode 1 bus master read cycle (cache line burst) 6-32 6.15 bus mode 1 bus master write cycle (noncache line burst) 6-36 6.16 bus mode 1 bus master write cycle (cache line burst) 6-37 6.17 bus mode 2 slave read cycle 6-41 6.18 bus mode 2 slave write cycle 6-45 6.19 bus mode 2 host bus arbitration 6-49 6.20 bus mode 2 fast arbitration 6-52 6.21 bus mode 2 bus master read cycle (noncache line burst) 6-56 6.22 bus mode 2 bus master read cycle (cache line burst) 6-57 6.23 bus mode 2 bus master write cycle (noncache line burst) 6-61 6.24 bus mode 2 bus master write cycle (cache line burst) 6-62 6.25 mux mode read cycle (noncache line burst) 6-65 6.26 mux mode read cycle (cache line burst) 6-65 6.27 mux mode write cycle (noncache line burst) 6-68 6.28 mux mode write cycle (cache line burst) 6-68 6.29 initiator asynchronous send 6-69 6.30 initiator asynchronous receive 6-69 6.31 target asynchronous send 6-70 6.32 target asynchronous receive 6-70 6.33 initiator and target synchronous transfers 6-71 c.1 160-pin pqfp (pz) mechanical drawing (sheet 1 of 2) c-1 d.1 divisor usage d-2
xii contents d.2 ti 75lbc976 differential transceiver d-5 d.3 symbios siop to 75lbc976 differential interface d-7 tables 2.1 parity control 2-5 2.2 big and little endian addressing 2-11 3.1 interface signals 3-3 4.1 register address map 4-2 4.2 examples of synchronous transfer periods and rates for scsi-1 4-13 4.3 examples of transfer periods and rates for fast scsi-2 4-13 4.4 synchronous scsi clock control bits 4-18 5.1 scsi information transfer phase 5-9 5.2 read/write instructions 5-20 5.3 transfer control instructions 5-23 5.4 scsi phase comparisons 5-25 6.1 absolute maximum stress ratings 6-2 6.2 operating conditions 6-2 6.3 scsi signals (open drain)?sd[7:0], sdp/, req/, msg/, i_o/, c_d/, atn/, ack/, bsy/, sel/, rst/ 6-3 6.4 input signals?bg/, boff/, reset/, cs/, bs, big-lit/, bclk, sclk 6-3 6.5 output signals (totem pole)?sdir[7:0], sdirp, bsydir, seldir, rstdir, tgs, igs 6-3 6.6 output signals (totem pole)?fetch/, irq/ 6-4 6.7 output signals (totem pole)?slack/, master 6-4 6.8 3-state output signals?a[31:6], fc[2:0], sc[1:0], upso-tt0/, cbreq/-tt1/, br/ 6-4 6.9 bidirectional signals (totem pole outputs)? a[5:0], d[31:0], dp[3:0], ds/-dle, as/-ts/, rw/, siz[1:0], berr/-tea/, halt/-tip/, bgack-bb/, cback/-tbi/, sterm/-ta/ 6-5 6.10 capacitance 6-5 6.11 tolerant active negation technology electrical characteristics 6-6 6.12 SYM53C710 bus mode 1 clock timings 6-10 6.13 SYM53C710 bus mode 2 clock timings 6-11
contents xiii 6.14 SYM53C710-1 bus mode 1 clock timings 6-11 6.15 SYM53C710-1 bus mode 2 clock timings 6-12 6.16 chip reset timings 6-12 6.17 irq timings 6-13 6.18 SYM53C710 bus mode 1 slave read timings 6-15 6.19 SYM53C710-1 bus mode 1 slave read timings 6-16 6.20 SYM53C710 bus mode 1 slave write timings 6-18 6.21 SYM53C710-1 bus mode 1 slave write timings 6-19 6.22 SYM53C710 bus mode 1 host bus arbitration timings 6-22 6.23 SYM53C710-1 bus mode 1 host bus arbitration timings 6-23 6.24 SYM53C710 bus mode 1 fast arbitration timings 6-26 6.25 SYM53C710-1 bus mode 1 fast arbitration timings 6-26 6.26 SYM53C710 bus mode 1 bus master read timings (noncache line and cache line burst) 6-29 6.27 SYM53C710-1 bus mode 1 bus master read timings (noncache line and cache line burst) 6-30 6.28 SYM53C710 bus mode 1 master write timings (noncache line and cache line burst) 6-34 6.29 SYM53C710-1 bus mode 1 bus master write timings (noncache line and cache line burst) 6-35 6.30 SYM53C710 bus mode 2 slave read timings 6-39 6.31 SYM53C710-1 bus mode 2 slave read timings 6-40 6.32 SYM53C710 bus mode 2 slave write timings 6-43 6.33 SYM53C710-1 bus mode 2 slave write timings 6-44 6.34 SYM53C710 bus mode 2 host bus arbitration timings 6-47 6.35 SYM53C710-1 bus mode 2 host bus arbitration timings 6-48 6.36 SYM53C710 bus mode 2 fast arbitration timings 6-51 6.37 SYM53C710-1 bus mode 2 fast arbitration timings 6-51 6.38 SYM53C710 bus mode 2 bus master cycle read timings (noncache line and cache line burst) 6-54 6.39 SYM53C710-1 bus mode 2 bus master read cycle timings (noncache line and cache line burst) 6-55 6.40 SYM53C710 bus mode 2 bus master write timings (noncache line and cache line burst) 6-59 6.41 SYM53C710-1 bus mode 2 bus master write timings (noncache line and cache line burst) 6-60 6.42 SYM53C710 bus mode 2 mux mode read timings 6-64 6.43 SYM53C710-1 bus mode 2 mux mode read timings 6-64
xiv contents 6.44 SYM53C710 bus mode 2 mux mode write timings 6-67 6.45 SYM53C710-1 bus mode 2 mux mode write timings 6-67 6.46 initiator asynchronous send timings 6-69 6.47 initiator asynchronous receive timings 6-69 6.48 target asynchronous send timings 6-70 6.49 target asynchronous receive timings 6-70 6.50 scsi-1 transfers (se 5.0 mbytes/s) 6-71 6.51 scsi-1 transfers (differential, 4.17 mbytes/s) 6-72 6.52 scsi-2 fast transfers (10.0 mbytes/s, 40 mhz clock) 6-72 6.53 scsi-2 fast transfers (10.0 mbytes/s, 50 mhz clock) 6-73 a.1 SYM53C710 register map a-1 b.1 new registers and bits b-2 b.2 deleted bits b-3 b.3 moved registers and bits b-3
symbios SYM53C710 scsi i/o processor 1-1 chapter 1 general description this chapter contains the following section: ? section 1.1, ?SYM53C710 features summary? the SYM53C710 is the second member of the sym53c700 family of intelligent, single chip, third generation scsi host adapters. a high-performance scsi core and an intelligent 32-bit bus master dma coreareintegratedwithascsiscripts?processortoaccommodate the flexibility requirements of scsi-1, scsi-2, and future scsi standards. the SYM53C710 solves the protocol overhead problems that have plagued all previous intelligent and nonintelligent adapter designs. the SYM53C710 is designed to completely implement a multithreaded i/o algorithm in either a workstation or file server environment, completely free of processor intervention except at the end of an i/o transfer. in addition, the SYM53C710 allows scsi scripts instructions to be relocated if necessary, and requires no dynamic alteration of scripts instructions at the start of an i/o operation. all of the scripts codemaybeplacedonaprom.theSYM53C710allowseasyfirmware upgrades and is scripts compatible with the sym53c700. the SYM53C710 supports two different host processor interfaces. bus mode 1 closely resembles the motorola 68030 interface, and bus mode 2 closely resembles the 68040 interface. the modes are selected by using the bus mode select pin. the SYM53C710 features symbios ? to l e r a n t ? active negation technology, which allows optional active negation of scsi signals during information transfer phases. when enabled, tolerant causes the scsi req, ack, data and parity signals to be actively pulled up to approximately three volts by transistors on each pin. the benefits of this technology include reduced noise when the signal is going high (deasserted), increased performance due to balanced duty cycles, and
1-2 general description improved fast scsi transfer rates. active negation is enabled by setting the ean bit in the chip test zero (ctest0) register. it can be used in both single-ended (se) and differential mode. tolerant is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. this manual provides descriptions and operational information for the SYM53C710 and SYM53C710-1. the SYM53C710 supports bus mode 1 (asynchronous) dma timings up to 25 mhz, and bus mode 2 (synchronous) dma timings up to 33 mhz. the SYM53C710-1 supports asynchronous timings up to 33 mhz and synchronous timings up to 40 mhz. electrical characteristics and timings for the SYM53C710 and SYM53C710-1 are provided in chapter 6, ?electrical specifications? . 1.1 SYM53C710 features summary this section provides an overview of the SYM53C710 features and benefits. it contains information on performance, integration, ease of use, flexibility, reliability, and testability. 1.1.1 performance ? supports variable block size and scatter/gather data transfers ? supports 32-bit word data bursts with variable burst lengths ? high-speed scsi bus transfers ? over 5 mbytes/s asynchronous ? 10 mbytes/s synchronous ? 42.66 mbytes/s sustained host bus bandwidth ? enhanced scripts capabilities ? relative jump ? table indirect data mode ? read/write system memory ? read/write registers ? arithmetic operations ? memory-to-memory dma transfers
SYM53C710 features summary 1-3 ? register parity during slave reads ? glitchless scsi on power-up/down ? minimizes scsi i/o start latency ? performs complex bus sequences without interrupts ? unique interrupt status reporting reduces interrupt service routine (isr) overhead ? cache line burst mode ? 64-byte dma fifo ? active negation of scsi data, parity req and ack signals with symbios tolerant technology improves rise times and fast scsi transfer rates in both se and differential modes 1.1.2 integration ? full 32-bit dma bus master ? high-performance scsi core ? integrated scripts processor ? allows intelligent host adapter performance on a motherboard 1.1.3 ease of use ? reduces scsi development effort ? emulates existing intelligent host adapters ? supportforbigandlittleendianbyteordering ? easily adapted to the scsi common access method (cam) by ?executing? data structures ? fullycompatiblewithexistingsym53c700scripts ? development tools and scsi scripts provided ? all interrupts are maskable and pollable 1.1.4 flexibility ? high level programmer?s interface (scsi scripts) ? allows tailored scsi sequences to be executed from main memory or from a host adapter board
1-4 general description ? flexible sequences to tune i/o performance or to adapt to unique scsi devices ? accommodates changes in the logical i/o interface definition ? low level programmability (register-oriented) ? allows a target to disconnect and later reselect the SYM53C710 with no interrupt to the system processor ? allows a multithreaded i/o algorithm to be executed in scsi scripts with a fast i/o context switch ? can autoswitch between initiator and target roles dynamically ? allows indirect fetching of dma address and byte counts so that scripts can be placed in a prom ? separate scsi and system clocks 1.1.5 reliability ? 2 kv minimum esd protection ? typical 350 mv scsi bus hysteresis ? protection against bus reflections due to impedance mismatches ? controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certification) ? latch-up protection greater than 150 ma ? 250 ms byte-to-byte scsi activity timer ? voltage feed-through protection (minimum leakage current through scsi pads) ? 20% of signals are power and ground ? ground isolation of i/o pads and chip logic 1.1.6 testability ? all scsi signals accessible through programmed i/o ? scsi loopback diagnostics ? self-selection capability ? scsi bus signal continuity checking
SYM53C710 features summary 1-5 figure 1.1 SYM53C710 block diagram scsi registers dma registers test registers scsi fifo sync control async control scsi sequences scripts processor slave i/o logic host bus master dma fifo (64-bytes) (8-bytes) scsi core dma core scsi data scsi control host data host control
1-6 general description
symbios SYM53C710 scsi i/o processor 2-1 chapter 2 functional description the SYM53C710 is composed of three tightly coupled functional blocks: the scsi core, the dma core, and the scripts processor. this chapter contains the following sections: ? section 2.1, ?scsi core? ? section 2.2, ?scripts processor? ? section 2.3, ?dma fifo? ? section 2.4, ?host interface? ? section 2.5, ?bidirectional sterm/_ta/? ? section 2.6, ?interrupts? ? section 2.7, ?scsi bus interface? 2.1 scsi core the scsi core supports synchronous transfer rates of up to 10 mbytes/s, and asynchronous transfer rates greater than 5 mbytes/s. the programmable scsi interface makes it easy to fine tune the system for specific mass storage devices or scsi-2 requirements. the scsi core offers low level register access or a high level control interface. like first generation scsi devices, the SYM53C710 scsi core is accessible as a register-oriented device. the ability to sample and/or assert any signal on the scsi bus is used in error recovery and diagnostic procedures. in support of loopback diagnostics, the scsi core performs a self-selection and operates as both an initiator and a target. the SYM53C710 tests the scsi pins for physical connection to the board or the scsi bus.
2-2 functional description unlike previous generation devices, the scsi core can be controlled by the integrated dma core through a high level logical interface. commands controlling the scsi core are fetched out of the main host memory. these commands instruct the scsi core to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases and in general, implement all aspects of the scsi protocol. 2.1.1 dma core the dma core is a bus master dma device that directly attaches to 68030 and 68040 processors, and to other processors (80386, 80486, etc.) with minimum logic. the SYM53C710 supports 32-bit memory and automatically supports misaligned dma transfers. a 64-byte fifo allows the SYM53C710 to support one, two, four, or eight longwords to be burst across the memory bus interface. this dma interface does not support dynamic bus sizing. the dma core is tightly coupled to the scsi core through the scripts processor which supports uninterrupted scatter/gather memory operations. 2.2 scripts processor the scripts processor is a special high speed processor optimized for scsi protocol. it allows both dma and scsi instructions to be fetched from host memory. algorithms written in scsi scripts can control the actions of the scsi and dma cores and are executed from 32-bit system memory. complex scsi bus sequences are executed independently of the host cpu. the scripts processor can begin a scsi i/o operation in approximately 500 ns. this compares with 2?8 ms required for traditional intelligent host adapters. the scripts processor offers performance and customized algorithms. algorithms may be designed to tune scsi bus performance, to adjust to new bus device types (i.e. scanners, communication gateways, etc.) or to incorporate changes in the scsi-2/scsi-3 logical bus definitions without sacrificing i/o performance.
scripts processor 2-3 2.2.1 loopback mode the SYM53C710 loopback mode allows testing of both initiator and target operations and, in effect, lets the chip talk to itself. when the loopback enable bit is set in the chip test four (ctest4) register, the SYM53C710 allows control of all scsi signals, whether the SYM53C710 is operating in initiator or target mode. 2.2.2 parity options the SYM53C710 implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and can deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. the following bits are involved in parity control and observation. control assert atn/ on parity errors (aap) ? bit 1 in the scsi control zero (scntl0) register. this bit causes the SYM53C710 to automatically assert scsi atn/ when it detects a parity error while operating as an initiator. enable parity generation (epg) ? bit 2 in the scsi control zero (scntl0) register. this bit determines whether the SYM53C710 generates parity sent to the scsi bus or allows parity to ?flow through? the chip to/from the scsi bus and system bus. enable parity checking (epc) ? bit 3 in the scsi control zero (scntl0) register. this bit enables the SYM53C710 to check for parity errors. the SYM53C710 checks for odd parity. assert even scsi parity (aesp) ? bit 2 in the scsi control one (scntl1) register. this bit determines the scsi parity sense generated by the SYM53C710. disable halt on atn/ or a parity error (dhp: target mode only) ? bit 7 in the scsi transfer (sxfer) register. this bit causes the SYM53C710 to immediately halt operations when a parity error is detected in target mode.
2-4 functional description enable parity error interrupt (par) ? bit 0 in the scsi interrupt enable (sien) register. this bit determines whether the SYM53C710 generates an interrupt when it detects a parity error. observation parity error ? bit 0 in the scsi status zero (sstat0) register. this status bit is set whenever the SYM53C710 detects a parity error on either the scsi bus or the system bus. status of scsi parity signal ? bit 0 in the scsi status one (sstat1) register. this status bit represents the live scsi parity signal (sdp/). latched scsi parity signal ? bit 3 in the scsi status two (sstat2) register. this status bit contains the scsi parity of the byte latched in the sidl. dma fifo parity ? bit 3 in the c h i p te s t tw o ( c t e s t 2 ) register. this status bit represents the parity bit in the dma fifo after data is read from the fifo by reading the chip test six (ctest6) register. dma fifo parity ? bit 3 in the chip test seven (ctest7) register. this write only bit is written to the dma fifo after writing data to the dma fifo by writing the chip test six (ctest6) register. scsi fifo parity ? bit 4 in the chip test two (ctest2) register. this status bit represents the parity bit in the scsi fifo after data is read from the fifo by reading the chip test three (ctest3) register.
scripts processor 2-5 table 2.1 parity control evp 1 epg 2 epc 3 aesp 4 description 000 0 does not check for parity errors. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data and host data. 000 1 does not check for parity errors. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts even parity when sending scsi data, odd parity when sending host data. 001 0 checks for odd parity on both scsi data received and system data when sending. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data and host data. 001 1 checks for odd parity on both scsi data received and system data when sending. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts even parity when sending scsi data, and odd parity when sending host data. 010 0 does not check for parity errors. parity on dp[2:0] is ignored and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip but is not asserted on dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data. 010 1 does not check for parity errors. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts even parity when sending scsi data. 011 0 checks for odd parity on scsi data received. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data. 011 1 checks for odd parity on scsi data received. parity on dp[2:0] is ignored and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts even parity when sending scsi data.
2-6 functional description 100 0 does not check for parity errors. parity flows from dp[2:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data, and even parity when sending host data. 100 1 does not check for parity errors. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts even parity when sending scsi data and host data. 101 0 checks for odd parity on scsi data received and even parity on system data when sending. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data and even parity when sending host data. 101 1 checks for odd parity on scsi data received and even parity on system data when sending. parity flows from dp[3:0] through the chip to the scsi bus when sending scsi data. parity flows from the scsi bus to dp[3:0] when receiving scsi data. asserts even parity when sending scsi data and host data. 110 0 does not check for parity errors. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip but is not asserted on dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data. 110 1 does not check for parity errors. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts even parity when sending scsi data. 111 0 checks for odd parity on scsi data received. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts odd parity when sending scsi data. 111 1 checks for odd parity on scsi data received. parity on dp[2:0] is ignored, and dp3 becomes abort/. parity is generated when sending scsi data. parity flows from the scsi bus to the chip, but is not asserted on dp[3:0] when receiving scsi data. asserts even parity when sending scsi data. 1. even parity. 2. enable parity generation. 3. enable parity checking. 4. assert scsi even parity. table 2.1 parity control (cont.) evp 1 epg 2 epc 3 aesp 4 description
dma fifo 2-7 2.3 dma fifo the dma fifo is a 64 x 9 bit fifo. it can be divided into four sections, each nine bits wide and 16 transfers deep as shown in figure 2.1 .each of these four sections are called byte lanes. each byte lane can be individually tested by writing known data into the fifo and reading that same data back out of the fifo. figure 2.1 dma fifo sections 2.3.1 interrupted transfer cleanup the data path through the SYM53C710 is dependent on whether data is being moved into or out of the chip, and whether scsi data is being transferred asynchronously or synchronously. figure 2.2 shows how data is moved to or from the scsi bus in each of the different modes. the following steps determine if any bytes remain in the data path when the chip halts an operation: 36-bits wide 16 transfers deep 9-bits byte lane 3 9-bits byte lane 2 9-bits byte lane 1 9-bits byte lane 0
2-8 functional description asynchronous scsi send ? use the algorithm described in the dma fifo (dfifo) register description ( chapter 4, ?registers? ) to determine if any bytes are left in the dma fifo. read the scsi status one (sstat1) register and examine bit 5 to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set, then there is abyteinthesodlregister. synchronous scsi send ? use the algorithm described in the dma fifo (dfifo) register description to determine if any bytes are left in the dma fifo. read the scsi status one (sstat1) register and examine bit 5 to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set, then there is a byte in the sodl register. read the scsi status one (sstat1) register and examine bit 6 to determine if any bytes are remaining in the sodr register. if bit 6 is set, then there is a byte in the sodr register. asynchronous scsi receive ? use the algorithm described in the dma fifo (dfifo) register description to determine if any bytes are left in the dma fifo. read the scsi status one (sstat1) register and examinebit7todetermineifabyteisleftinthe scsi input data latch (sidl) register. if bit 7 is set, then there is a byte in the sidl register. synchronous scsi receive ? use the algorithm described in the dma fifo (dfifo) register description to determine if any bytes are left in the dma fifo. read the scsi status two (sstat2) register and examine bits [7:4], the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo.
host interface 2-9 figure 2.2 SYM53C710 data paths 2.4 host interface 2.4.1 big/little endian support the big/little endian mode select pin gives the SYM53C710 the flexibility of operating with either byte orientation. internally, in either mode, the byte lanes of the dma fifo and registers are not modified. when a longword is accessed, no repositioning of the individual bytes is necessary, since longwords are addressed identically in either mode. longwords are always used by scripts, compatibility is maintained. big/little endian mode selection has the most effect on individual byte access. internally, the SYM53C710 adjusts the byte control logic of the dma fifo and register decodes to access the appropriate byte lane. the registers always appear on the same byte lane, but the address of the register is repositioned. data to be transferred between system memory and the scsi bus always starts at address zero and continues through address ?n??there is no byte ordering in the chip. the first byte in from the scsi bus goes p interface p interface p interface p interface dma fifo (36-bits x 16) dma fifo (36-bits x 16) dma fifo (36-bits x 16) dma fifo (36-bits x 16) sodl register sidl register sodr register sodl register scsi interface scsi interface scsi interface scsi interface scsi fifo (9-bits x 8) asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive
2-10 functional description to address 0, the second to address 1, etc. going out onto the scsi bus, address 0 is the first byte out on the scsi bus, address 1 is the second byte, etc. correct scripts is generated if the scripts compiler is run on a system that has the same byte ordering as the target system. any scripts patching in memory must patch the instructions in the order that the scripts processor expects it. software drivers for the SYM53C710 should access registers by their logical name (i.e., ?scntl0?) rather than by their address. the logical name should be equated to the register?s big endian address in big endian mode (scntl0 = 0x03), and its little endian address in little endian mode (scntl0 = 0x00). this way, there is no change to the software when moving from one mode to the other; only the equate file needs to be changed. addressing of registers from within a scripts is independent of bus mode. internally, the SYM53C710 always operates in little endian mode. 2.4.2 big endian mode big endian addressing is used primarily in designs based on motorola processors. the SYM53C710 treats d[31:24] as the lowest physical memory address. the register map is left justified (address 0x03 = scntl0) as detailed below. 2.4.3 little endian mode little endian is used primarily in designs based on intel processors. this mode treats d[7:0] as the lowest physical memory address. the register map is right justified (address 0x00 = scntl0) as detailed below.
host interface 2-11 2.4.4 misaligned transfers the SYM53C710 accommodates block data transfers beginning or ending on odd byte or odd word addresses in system memory. such transfers are termed ?misaligned.? an odd byte is defined as one in which the address contains a0 = 1. an odd word is defined as one in which the address contains a1 = 1. misaligned transfers differ depending on the type of transfer (cache line or programming bursting) and whether they occur at the start or end of the transfer. note: the SYM53C710 does not perform 3-byte transfers. 2.4.5 cache line bursting if cache line bursting is supported by the external memory device, it can be used to reduce host bus ownership by the SYM53C710, thereby improving system performance. during cache line burst mode, the handshaking that occurs between the memory system and the SYM53C710 is minimized, reducing host bus activity and allowing more time for other bus masters to gain access to the host bus. during caching mode, the SYM53C710 asserts one address and reads/writes four longwords of data with minimal handshaking (see chapter 6, ?electrical specifications? for cache line burst timings). cache line burst mode is enabled in the SYM53C710 by clearing bit 7 in ctest7. when using cache line burst mode, the burst length in dmode must be set to 4. table 2.2 big and little endian addressing system data bus [31:24] [23:16] [15:8] [7:0] SYM53C710 pins [31:24] [23:16] [15:8] [7:0] register sien sdid scntl1 scntl0 little endian addr 0x03 0x02 0x01 0x00 bigendianaddr 0x00 0x01 0x02 0x03
2-12 functional description caution: the chip will not perform correctly if the burst length is set to 1, 2 or 8, while caching is enabled. 2.4.6 cache line burst with start of transfer misaligned at the start of the transfer, if the address starts at an odd byte boundary (address bit a0 = 1), the SYM53C710 lines up to a word boundary by performing a single byte (8-bit) transfer in a single bus ownership. then, if the address is at an odd word boundary (address bit a1 = 1), the SYM53C710 lines up to a longword boundary by performing a single word (2-byte) transfer in a single bus ownership. at this point, a longword (4-byte) transfer is performed, one per bus ownership, until the address bits line up to a cache line boundary (a[3:0] = 0). once aligned, cache line bursts of four longwords per bus ownership are performed until the byte count decreases to 31 or less. the worst case example of five bus ownerships before cache line bursting can begin is depicted in little endianmodein figure 2.3 .
host interface 2-13 figure 2.3 cache line bursting, start of transfer (little endian mode) 2.4.7 cache line burst with end of transfer misaligned when the byte count decreases to 31 or fewer bytes, the SYM53C710 drops out of cache burst mode and transfers the remaining longwords, words, and/or bytes in one or more bus ownerships until the transfer is complete. the SYM53C710 transfers longwords until the byte count decreases to 3 or less. if the byte count is 3 or 2, one word is transferred. if the byte count is 1, one byte is transferred. an example depicting the SYM53C710 dropping out of cache line burst mode with the byte count decreasing to 31 is shown in figure 2.4 . 01 10 11 1 (siz=01) 2 (siz=10) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 address bits [a5:a2] address bits [a1:a0] 00 at least 32 bytes remain to be transferred at this point. notes: a) this transfer begins at address 000001. b) the start of this transfer requires five bus ownerships before caching can begin. c) cache line bursting continues after bus ownership #6 until the byte count decreases to 31 or less. see figure 2.2 for end of transfer. d) 1 (siz=01) denotes a single bus ownership. e) ?siz=01? denotes the siz[1:0] bit values. 3 (siz=00) 4 (siz=00) 5 (siz=00) 6 (siz=11inmode2 siz=00 in mode 1) 7 (siz=11inmode2 siz=00 in mode 1)
2-14 functional description note: when doing cache line bursting during a memory-to- memory move operation, the lower four address bits [a3:a0] of the source and destination must be equal. cache line bursting will not start until [a3:a0] are zero. figure 2.4 cache line bursting, end of transfer (little endian mode) 01 10 11 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 address bits [a5:a2] address bits [a1:a0] 00 at this point, less than 32 bytes remain to be transferred. 4 (siz=01) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) one ownership: burst mode. one ownership: nonburst. 1 (siz=11 in mode 2 siz=00 in mode 1) 2 3 (siz=10)
host interface 2-15 2.4.8 programmable bursting the SYM53C710 performs programmable bursting when bit 7 in ctest7 is set. in this mode, the SYM53C710 can perform 1, 2, 4 or 8 transfers per bus ownership, depending on the burst length value in the dma mode (dmode) register. the transfers can be byte, word, or longword transfers, depending on the data alignment. during programmable burst mode, one ts/ is asserted per transfer, i.e., there is a complete handshake between the memory device and the SYM53C710 for each transfer. 2.4.9 programmable burst with start of transfer misaligned the SYM53C710 transfers the programmable burst length number of transfers during each bus ownership. if the address starts at an odd byte boundary (bit a0 = 1), the SYM53C710 lines up to a word boundary by performing a single byte transfer. if a1 = 1, the SYM53C710 performs a word transfer. at this point, the SYM53C710 transfers longwords until the byte count decreases to 3 or less. the chip transfers the programmable burst length number of transfers per bus ownership regardless of the width (byte, word or longword). an example of a transfer in which the programmable burst length is 8 is depicted in figure 2.5 .
2-16 functional description figure 2.5 programming bursting, start of transfer (little endian mode) 01 10 11 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 address bits [a5:a2] address bits [a1:a0] 00 (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) 2 (siz=01) (siz=10) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) 1 (siz=00) (siz=00) 1100 1101 1110 note: this transfer (programmable burst length = 8) involves two bus ownerships.
host interface 2-17 2.4.10 programmable burst with end of transfer misaligned the SYM53C710 transfers longwords until the byte count decreases to 3 or less. if the byte count is 3 or 2, one word is transferred. if the byte count is 1, one byte is transferred. the SYM53C710 transfers the programmable burst length number of transfers per bus ownership. at the end of a block transfer, if the byte count is less than the programmable burst length, the remaining bytes are transferred during the bus ownership. it is possible to transfer less but not more than the programmable burst length number of transfers per bus ownership. an example of a transfer in which the programmable burst length is 8 is depicted in figure 2.6 . note: each bus ownership requires the SYM53C710 to arbitrate for the host bus. there is a fairness delay of 5 ? 8clocks between each bus ownership.
2-18 functional description figure 2.6 programming bursting, start of transfer (little endian mode) 2.4.11 host bus retry host bus retry allows the SYM53C710 to retry the previous cycle using the same address, size, etc. the bus retry signals are asserted by an external device using the halt/ (halt) and berr/ (bus error) signals in bus mode 1, and ta/ (transfer acknowledge) and tea/ (transfer error acknowledge) in bus mode 2. during a noncache line burst, a bus retry canbeexecutedinanycycle.duringacachelineburst,however,the bus retry should be executed during the ack portion of the first transfer in the first cycle. in both bus modes, the SYM53C710 retries the bus cycle and asserts the cbreq/ (cache burst request) again. if a bus retry is attempted during one of the subsequent cycles, the SYM53C710 halts with a bus error status. 01 10 11 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 address bits [a5:a2] address bits [a1:a0] 00 (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) (siz=00) 2 (siz=10) (siz=00) (siz=00) (siz=00) 1 (siz=00) (siz=00) note: (siz=01) this transfer (programmable burst length = 8) involves two bus ownerships.
bidirectional sterm/_ta/ 2-19 2.5 bidirectional sterm/_ta/ the sterm/_ta/ signal terminates a read or write cycle. in a typical system, sterm/_ta/ is a wired-or signal driven by slave devices and monitored by bus masters. when the system cpu is faster than the slave device being accessed, a cycle may be terminated as soon as the slave is ready. slave devices which are faster than the cpu present a special problem in that they are required to insert wait states to allow the cpu to catch up. the SYM53C710 is able to accommodate both situations. during slave accesses, the slack/ output provides an indication that the SYM53C710 is ready to terminate a read or write cycle. after asserting slack/, the SYM53C710 samples sterm/_ta/ on every subsequent rising bclk edge until it is sampled active, at which time the read/write cycle is terminated. any time between slack/ and sterm/_ta/ is treated as a wait state; a read/write cycle may be stretched indefinitely, but write data must be valid by the second clock cycle after chip select is sampled true. typically, slack/ is tied back to sterm/_ta/ as in figure 2.7 .ifthe system cpu is not capable of completing a slave cycle in the minimum time required by the SYM53C710, slack/ must be delayed before asserting sterm/_ta/. if the system cpu is capable of running slave read/write cycles with zero additional wait states, no delay is necessary. in systems where the cpu is faster than the SYM53C710, slack/ may be connected to sterm/_ta/ with external logic, but the best solution is to set the enable acknowledge (ea) bit in the dma control (dcntl) to internally connect slack/ to sterm_ta/. when the ea bit is set, the sterm/_ta/ pin changes from being an input in both master and slave modes, and becomes bidirectional: input in master mode, and output in slave mode. this way, no external logic is required and proper timing is guaranteed. setting the ea bit must be the first slave i/o access to the SYM53C710. in addition, when the ea bit is set, a signal with the same timing characteristics as slack/ is driven onto the sterm/_ta/ pin, as illustrated in figure 2.7 . the external timing on this signal is the same as the signal generated if ea was not used, as illustrated in figure 2.8 .the additional control logic 3-states sterm/_ta/ for 5 ns after it is deasserted. the slack/ signal is always driven.
2-20 functional description figure 2.7 slack/ tied back to sterm/_ta/ (ea bit not set) figure 2.8 bidirectional sterm/ (ea bit set) sterm/_ta/ SYM53C710 slack/ pa l d e l ay open collector sterm/_ta/ 5v 470 additional control ea into chip slack/ internal slack/ sterm/_ta/ 470 5v SYM53C710
interrupts 2-21 2.6 interrupts 2.6.1 polling vs. hardware interrupts the external microprocessor can be informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used by other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the SYM53C710 asserts the interrupt request (irq/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine (isr). a hybrid approach would use hardware for long waits, and use polling for short waits. 2.6.2 registers the five registers in the SYM53C710 that are used for detecting or defining interrupts are interrupt status (istat) , scsi status zero (sstat0) , dma status (dstat) , scsi interrupt enable (sien) and dma interrupt enable (dien) . istat ? the interrupt status (istat) is the only register that can be accessed as a slave during scripts operation. therefore, it is the register that is polled when polled interrupts are used. it is also the first register that should be read after the irq/ pin is asserted in association with a hardware interrupt. if the sip bit in the istat register is set, then a scsi-type interrupt occurs and the scsi status zero (sstat0) register should be read. if the dip bit in the istat register is set, then a dma-type interrupt occurs and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases bothsipanddipmaybeset. sstat0 ? the scsi status zero (sstat0) register contains the scsi-type interrupt bits. reading this register determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition.
2-22 functional description if the SYM53C710 is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. if the SYM53C710 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. because of this the dfe (dma fifo empty) bit in dma status (dstat) should be checked. if this bit is cleared, set the clf (clear dma and scsi fifos) bit before continuing. dstat ? the dma status (dstat) register contains the dma-type interrupt bits. reading this register determines which condition or conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7 in dstat, dfe, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read. dma interrupts flush neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dstat register should be checked after any dma interrupt. if the dfe bit is cleared, then the fifos must be cleared by setting the clf (clear dma and scsi fifos) bit (bit 2 in the chip test eight (ctest8)) register, or flushed by setting the flf (flush dma fifo) bit (bit 3 in the ctest8 register). sien ? the scsi interrupt enable (sien) register is the interrupt enable register for the scsi interrupts in scsi status zero (sstat0) . dien ? the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . 2.6.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes scripts to stop running. a nonfatal interrupt causes scripts to stop running only if it is not masked. masking is discussed later in this technical manual. all dma interrupts (indicated by the dip bit in interrupt status (istat) and one or more bits in dma status (dstat) being set) are fatal. some scsi interrupts (indicated by the sip bit in the interrupt status (istat) and one or more bits in scsi status zero (sstat0) being set) are nonfatal.
interrupts 2-23 when the chip is operating in initiator mode, only the function complete (cmp) and selected or reselected (sel) interrupts are nonfatal. when operating in target mode cmp, sel, and m/a (target mode: atn/ active) are nonfatal. refer to the description for the disable halt on a parityerrororatn/active(targetmodeonly)(dhp)bitinthe scsi transfer (sxfer) register to configure the chip?s behavior when the atn/ interrupt is enabled during target mode operation. the reason for nonfatal interrupts is to prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the SYM53C710 is selected or reselected (sel set), or when the initiator has asserted atn (target mode: atn/ active). these interrupts are not needed for events that occur during high level scripts operation. 2.6.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts canbemaskedbyclearingbitsinthe scsi interrupt enable (sien) (for scsi interrupts) register or dma interrupt enable (dien) (for dma interrupts) register. how the chip responds to masked interrupts depends on whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, scripts does not stop, the appropriate bit in the scsi status zero (sstat0) is set, the sip bit in the interrupt status (istat) is not set, and the irq/ pin is not asserted. see section 2.6.3, ?fatal vs. nonfatal interrupts? for a list of the nonfatal interrupts. if a fatal interrupt is masked and that condition occurs, then scripts still stops. the appropriate bit in the dma status (dstat) or scsi status zero (sstat0) register is set, the sip or dip bits in the interrupt status (istat) is set, and the irq/ pin is not asserted. when the SYM53C710 is initialized, enable all fatal interrupts if hardware interrupts are being used. if a fatal interrupt is disabled and that interrupt condition occurs, scripts halts and the system never knows it unless it times out and checks the interrupt status (istat) after a certain period of inactivity.
2-24 functional description if istat is being polled instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the interrupt status (istat) inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted does not cause deassertion of irq/. 2.6.5 stacked interrupts the SYM53C710 will stack interrupts, if they occur, one after the other. if the sip or dip bits in the interrupt status (istat) register are set (first level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the scsi status zero (sstat0) and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind sstat0 and dstat. when the first level of interrupts are cleared, all the interrupts that came in afterward move into the sstat0 and dstat. after the first interrupt is cleared by reading the appropriate register, the irq/ pin is deasserted for a set time as published in the product technical manual; the stacked interrupt(s) move into the sstat0 or dstat; and the irq/ pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in scsi status zero (sstat0) butdoesnotasserttheirq/ pin. since no interrupt is generated, future interrupts move into the scsi status zero (sstat0) instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to flush the fifos before generating the interrupt. it is important to set either the clear dma and scsi fifos (clf) bit or the flush dma fifo (flf) bit
interrupts 2-25 if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these ?locked out? scsi interrupts are posted as soon as the dma fifo is empty. 2.6.6 halting in an orderly fashion when an interrupt occurs, the SYM53C710 attempts to halt in an orderly fashion. ? if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault or watchdog time-out. execution does not begin, but the dsp points to the next instruction since it is updated when the current scripts is fetched. ? if the dma direction is a write to memory and a scsi interrupt occurs, the SYM53C710 attempts to flush the dma fifo to memory before halting. under any other circumstances only the current cycle is completed before halting, so the dfe bit in dma status (dstat) should be checked to see if any data remains in the dma fifo. ? scsi req/ack handshakes that have begun are completed before halting. ? the SYM53C710 attempts to clean up any outstanding synchronous offset before halting. ? in the case of transfer control instructions, once instruction execution begins it continues to completion before halting. ? if the instruction is a jump/call when , the dma scripts pointer (dsp) is updated to the transfer address before halting. ? all other instructions may halt before completion. 2.6.7 sample interrupt service routine the following is a sample of an isr for the SYM53C710. it can be repeated if polling is used, or should be called when the irq/ pin is asserted if hardware interrupts are used. 1. read interrupt status (istat) . 2. if only the sip bit is set, read scsi status zero (sstat0) to clear the scsi interrupt condition and get the scsi interrupt status. the
2-26 functional description bits in the sstat0 tell which scsi interrupts occurred and determine what action is required to service the interrupts. 3. if only the dip bit is set, read dma status (dstat) to clear the interrupt condition and get the dma interrupt status. the bits in dstat tell which dma interrupts occurred and determine what action is required to service the interrupts. 4. if both the sip and dip bits are set, read scsi status zero (sstat0) and dma status (dstat) to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of sstat0 and dstat registers to clear interrupts, insert a 12 clock delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the isr. it is recommended that the dma interrupt be serviced before the scsi interrupt, because a serious dma interrupt condition could influence how the scsi interrupt is acted upon. 5. when using polled interrupts go back to step 1 before leaving the isr in case any stacked interrupts moved in when the first interrupt was cleared. when using hardware interrupts, the irq/ pin is asserted again if there are any stacked interrupts. this should cause the system to re-enter the isr. 2.7 scsi bus interface the SYM53C710 can be used in both se and differential applications. in se mode, all scsi signals are active low. the SYM53C710 contains open drain output drivers that can be connected directly to the scsi bus. each output is isolated from the power supply to ensure that a powered down SYM53C710 has no effect on an active scsi bus (cmos ?voltage feed-through? phenomenon). additionally, signal filtering is present at the inputs of req/ and ack/ to increase immunity to signal reflections. in differential mode, the sdir [7:0], sdirp, igs, tgs, rstdir, bsydir, and seldir signals control the direction of external differential pair transceivers. see figure 2.9 for the suggested differential wiring diagram. please refer to appendix d for more information. the wiring diagram shows five 75als170 3-channel transceivers and one 75als171 3-channel transceiver, though other single and multichannel
scsi bus interface 2-27 devices may be used (ds36954 4-channel transceiver, for instance). the suggested value for the 15 pull-up resistors in the diagram is 680 ? .if active negation is enabled and the chip is operating in differential mode, the value of the pull-up resistors should be 1.5 k ? . refer to appendix d for other differential interface options. 2.7.1 terminator networks the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and are required for both se and differential applications. terminators must be installed at the extreme ends of the scsi cable, and only at the ends. no system should ever have more or less than two sets of terminators installed and active. scsi host adapters should provide a means of accommodating terminators. there should be a means of disabling the termination. se cables can use a 220 ? pull-up resistor to the termination power supply (term power) line and a 330 ? pull-down resistor to ground. differential cables use a 330 ? pull-up resistor from ?? sig? to term power, a 330 ? pull-down resistor from ?+ sig? to ground, and a 150 ? resistor from ?? sig? to ?+ sig?. because of the high-performance nature of the SYM53C710, alternative two se termination is recommended. this method employs a 2.85 v regulator and 110 ? pull-up resistors (no pull-down). figure 2.10 and figure 2.11 show two examples of schematics for alternative two termination. for more information on alternative two termination, refer to the scsi-2 specification. 2.7.2 select/reselect during selection/reselection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this situation may occur when a scsi controller (operating in initiator mode) tries to select one target and is reselected by another. the analogous situation for target devices is being selected while trying to perform a reselection. the SYM53C710 can handle this condition in a manner identical to the sym53c700, that is, autoswitching between initiator and target modes, but the recommended method is to disable the autoswitching utility.
2-28 functional description when autoswitching is enabled, regardless of the current operating mode (initiator or target), if the SYM53C710 becomes reselected while executing a select/reselect instruction, then it autoswitches to initiator mode. similarly, if the SYM53C710 becomes selected while executing a select/reselect instruction, it autoswitches to target mode. after the automatic mode switch, the SYM53C710 fetches the next instruction from the alternate address, pointed to by the dma next data address (dnad) register (the second 32-bit word of the select/reselect instruction). the recommended method of handling selection/reselection during selection/reselection is to disable autoswitching and put a set target instruction at the start of the target scripts (before the wait select code). 2.7.3 synchronous operation the SYM53C710 can transfer synchronous scsi data in both initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it may be loaded by the cpu before scripts execution begins, or from within scripts using a table indirect i/o instruction. the SYM53C710 can receive data at a synchronous transfer period of 100/200 ns (scsi-2/scsi-1), regardless of the transfer period used to send data. therefore, when negotiating for synchronous data transfers, the suggested transfer period is 100/200 ns. depending on the sclk frequency, the SYM53C710 can send synchronous data at intervals as short as 100/200 ns.
scsi bus interface 2-29 figure 2.9 differential wiring diagram a b + ? +5v a b + ? +5v a b + ? +5v sdir0 sd0 sd2 sdir1 sd1 75als170 sdir2 a b + ? +5v a b + ? +5v a b + ? +5v sdir3 sd3 sd5 sdir4 sd4 sdir5 a b + ? +5v a b + ? +5v a b + ? +5v sdir6 sd6 sdp sdir7 sd7 sdirp a b + ? +5v a b + ? +5v a b + ? +5v c/d req i/o a b + ? +5v a b + ? +5v a b + ? +5v ack msg igs at n tgs a b + ? seldir sel bsydir a b + ? bsy a b + ? rstdir rst 75als171
2-30 functional description figure 2.10 alternative two termination (example 1) sdo (j1.2) sd1 (j1.4) sd2 (j1.6) sd3 (j1.8) sd4 (j1.10) sd5 (j1.12) sd6 (j1.14) sd7 (j1.16) sdp (j1.18) atn (j1.32) bsy (j1.36) ack (j1.38) rst (j1.40) msg (j1.42) sel (j1.44) c/d (j1.46) req (j1.48) i/o (j1.50) lt 1086 vdd c1 c2 c3 c4 c5 r1 r2 u1 d1 f1 d2 j1.26 (termpwr) w1 note: ? c1 = 47 f tantalum, smt ? c2, c3 = 1.0 f tantalum, smt ? c4 = 2.2 f tantalum, smt ? c5 = 0.1 f ceramic, smt ? d1, d2 = schottky diode, 1n5817 ? f1 = 1.5 amp fuse, socketed, 2ag ? j1 = 50-pin dual row header, male scsi connector ? rp1, rp2 = 110 = ? x 9 pull-ups, 1% sip-10 ? u1 = voltage regulator lt 1086, to-39 ? w1 = 2 position jumper rp1 rp2
scsi bus interface 2-31 figure 2.11 alternative two termination (example 2) terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 terml10 terml11 terml12 terml13 terml14 terml15 terml16 terml17 terml18 sd0 (j1.2) sd1 (j1.4) sd2 (j1.6) sd3 (j1.8) sd4 (j1.10) sd5 (j1.12) sd6 (j1.14) sd7 (j1.16) sdp (j1.18) atn (j1.32) bsy (j1.36) ack (j1.38) rst (j1.40) msg (j1.42) sel (j1.44) c/d (j1.46) req (j1.48) i/o (j1.50) 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 19 disconnect reg_out 2 2.85 v uc5601qp c1 c2 note: ? c1 = 10 f tantalum, smt ? c2 = 0.1 f ceramic, smt ? j1 = 50-pin dual row header, male scsi connector
2-32 functional description
symbios SYM53C710 scsi i/o processor 3-1 chapter 3 signal descriptions the SYM53C710 host bus can operate in one of two modes: bus mode 1 (asynchronous) and bus mode 2 (synchronous). the bus mode is selected with the bus select pin. the signal types are abbreviated as follows: ?i? for input, ?o? for output, and ?z? for high impedance. a slash (?/?) indicates an active low signal. refer to the section 6.1, ?dc characteristics? for specific pin type (3-state, open drain, etc.) and current drive capabilities.
3-2 signal descriptions figure 3.1 SYM53C710 pin configuration a14 a15 a17 a19 a21 v ss a26 a27 v ss as/-ts/ siz0 fc2-tm2 upso-tto/ berr/-tea/ master/ v dd 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 a22 a24 v ss cbreq/-tti/ quad flat pack 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 v ss a16 a18 a20 a23 a25 a29 a30 siz1 fc0-tm0 r_w/ sterm/-ta/ v dd v ss v dd a28 a31 fc1-tm1 cback/-tbi/ halt/-tip/ at n / v ss rst/ v ss i/o seldir igs tgs v dd v ss reset/ cs/ ds/-dle d1 d2 v ss 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 85 84 83 82 81 v ss rstdir big_lit/ sc0 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 bsy/ ack/ sel/ req/ bsydir irq/ bg/ bgack/-bb/ boff/ bs sc1 d0 msg/ c/d sclk br/ fetch/ slack/ dp0 d3 bclk d30 d28 d26 d24 d22 d20 d19 d16 d15 d13 d12 dp1 d6 d5 v dd dp3_abrt/ v ss d10 d8 d31 d29 d27 d25 d23 d21 v ss dp2 d14 d11 d9 d7 v ss v dd d18 d17 v dd v ss v ss v ss sd5/ sd4/ sd1/ sdir7 sdir5 v ss sdir0 a1 a2 a3 v ss a5 a6 a8 121 123 125 127 129 131 133 135 137 139 141 143 144 145 146 147 148 150 152 154 156 158 sd7/ v dd srir1 a7 v dd v ss a10 a13 160 a12 122 124 126 128 130 132 134 136 138 140 142 149 151 153 155 157 159 sdp/ sd6/ sd2/ sd0/ sdir6 sdir3 sdir2 a0 sd3/ v ss sdirp sdir4 v ss a4 a9 a11 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 76 77 78 79 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 scsi i/o processor 160-pin d4 (top view)
3-3 table 3.1 interface signals bus mode 1 bus mode 2 slave type master type description (slave type, master type) d[31:0] d[31:0] i/o i/o host data bus . main 32-bit data path into host memory. dp[3:0] dp[3:0] i/o i/o host bus data parity . dp0 provides parity for d[7:0], dp1 for d[15:8], etc. parity is valid on all byte lanes, including unused lanes. when the parity through mode is disabled, dp3 becomes a hardware abort input (abrt/). ds/ dle z i o i data strobe, data latch enable . ds/: in bus mode 1, this signal indicates that a valid data has been or should be placed on the data lines. dle: latches read data into the SYM53C710 when operating in bus mode 2. data latches are transparent when dle is high. this signal is used to address host memory and internal registers. this signal should be pulled high if not used. a[31:0] a[31:0] i o address bus . these signals provide an address bus to the host memory. as/ ts/ i o address strobe, transfer start. as/: in bus mode 1, this signal indicates that a valid address is on a[31:0]. ts/: in bus mode 2, transfer start indicates that a bus cycle is starting and all of the status and address lines are valid. r_w/ r_w/ i o read/write . indicates the direction of the data transfer relative to the current master. siz[1:0] siz[1:0] i o transfer size . indicates the current transfer width. 00 - longword (4 bytes) 01 - byte (1 byte) 10 - word 11 - bus mode 1: illegal in slave mode, will not occur in master bus mode 2: cache line burst
3-4 signal descriptions sterm/ ta/ i/o i synchronous cycle termination, transfer acknowledge . sterm/: acknowledges transfer to a 32-bit wide port. when the ea bit in the dma control (dcntl) is set, this signal becomes bidirectional: input in master mode and output in slave mode. ta/: acknowledges transfer to a 32-bit wide port. when the ea bit in the dma control (dcntl) is set, this signal becomes bidirectional: input in master mode and output in slave mode. berr/ tea/ o i bus error acknowledge, transfer error acknowledge. berr/: indicates that a bus fault has occurred. may be used with halt/ to force a bus retry. tea/: indicates that a bus fault has occurred. halt/ tip/ z z i o halt, transfer in progress. halt/: input only, used with berr/ to indicate a bus retry cycle. tip/: bidirectional, indicates that bus activity is in progress. slack/ slack/ o o slave acknowledge . when asserted, indicates the internal end of a slave mode cycle. the external slave cycle ends when the SYM53C710 observes either sterm/_ta/ or berr/-tea/. fc[2:0] tm[2:0] z o function codes, transfer modifiers. indicates the status of the current bus cycle. fc0, tm0 = 1: indicates data space; it is the default for all transfers fc0, tm0 = 0: indicates program space. it may be optionally selected when setting the pd bit in the dma mode (dmode) register fc1, tm1: user definable from the dmode register bits fc2, tm2: user definable from the dmode register bits sc[1:0] sc[1:0] z(o) o snoop control . indicates the bus snooping level. the bits are user programmable through bits in the chip test seven (ctest7) register. they are asserted when the SYM53C710 is the bus master. (sc[1:0] may optionally be used as pure outputs, active in both master and slave modes. see the chip test eight (ctest8) register description for use of sc[1:0] as pure outputs.) master/ master/ o o master status . driven low when the SYM53C710 becomes bus master. table 3.1 interface signals (cont.) bus mode 1 bus mode 2 slave type master type description (slave type, master type)
3-5 fetch/ fetch/ o o fetching opcode . indicates that the next bus request will be for an opcode fetch. br/ br/ o o bus request . indicates that there is a request to use the host bus. bg/ bg/ i i bus grant . indicates that the host bus has been granted to the SYM53C710. bgack/ bb/ z i/o bus grant acknowledge, bus busy (can be wired-or). bgack/: in bus mode 1, this signal indicates that the SYM53C710 or another device has taken control of the host bus signals. bb/: in bus mode 2, this signal indicates that the SYM53C710 or another device has taken control of the host bus signals. boff/ boff/ i i back off . forces the SYM53C710 to relinquish bus mastership at the end of the current cycle, if the proper setup timing requirements are met. when boff is deasserted, a new arbitration cycle will occur and bus cycles will resume. bclk bclk i i bus clock . this clock controls all host related activity. reset/ reset/ i i chip reset . forces a full chip reset. cs/ cs/ i i chip select . selects the SYM53C710 as a slave i/o device. when cs/ is detected: bus mode 1: cback/ is deasserted bus mode 2: tbi/ is asserted irq/ irq/ o o interrupt. indicates that service is required from the host cpu. upso tt0/ z o user programmable status, transfer type zero. upso: general purpose line. the value in a dma mode (dmode) register bit is asserted while the chip is a bus master. tt0: indicates the current bus transfer type. this bit can be programmed from a register bit (default = 0). it is asserted only when the SYM53C710 is bus master. table 3.1 interface signals (cont.) bus mode 1 bus mode 2 slave type master type description (slave type, master type)
3-6 signal descriptions cbreq/ tt1/ z o cache burst request, transfer type bit 1 . cbreq/: in bus mode 1, cache burst request indicates an attempt to execute a line transfer of four longwords. tt1/: in bus mode 2, transfer type bit 1, output line indicates the current bus transfer type. this bit can be programmed from a chip test seven (ctest7) register bit (default = 1). it is only asserted when the SYM53C710 is bus master. cback/ tbi/ o i cache burst acknowledge, transfer burst inhibit . cback/: in bus mode 1, this signal indicates that the memory can handle a burst request. in slave mode this signal is deasserted in response to cs/. tbi/: in bus mode 2, transfer burst inhibit indicates that the memory cannot currently handle a burst request. in slave mode this signal is asserted in response to cs/. bs bs i i bus mode select . selects between asynchronous and synchronous host bus modes. bs = 0: bus mode 2 (68040-like) host bus mode bs = 1: bus mode 1 (68030-like) host bus mode big_lit/ big_lit/ i i big/little endian select . selects the byte order interpretation of data transferred between the host and scsi bus. it also affects how the register set is addressed. big_lit/ = 0: little endian byte order big_lit/ = 1: big endian byte order sclk sclk i i scsi clock .sclkisusedtoderiveallscsirelated timings. the speed of this clock will be determined by the application?s requirements; in some applications sclk and bclk may be tied to the same source. sd[7:0] sdp/ i/o i/o scsi data . sd/[7:0]: 8-bit scsi data bus sdp/: scsi data parity bit table 3.1 interface signals (cont.) bus mode 1 bus mode 2 slave type master type description (slave type, master type)
3-7 sctrl/ sctrl/ i/o i/o scsi control . cd/ scsi phase line, command/data io / scsi phase line, input/output msg / scsi phase line, message req / data handshake signal from target device ack / data handshake signal from initiator device at n / scsi bus attention signal bsy / 1 scsi bus arbitration signal, signal busy sel/ 1 scsi bus arbitration signal, select device rst / 1 scsi bus reset sdir[7:0] sdir[7:0] o o differential support lines . driver direction control for scsi data lines. sdirp sdirp o o differential support line . driver direction control for scsi parity signal. bsydir bsydir o o differential support line . driver enable control for scsi bsy/ signal. seldir seldir o o differential support line . driver enable control for scsi sel/ signal. rstdir rstdir o o differential support line . driver enable control for scsi rst/ signal. igs igs o o differential support line . direction control for initiator driver group. tgs tgs o o differential support line . direction control for target driver group. 1. input only in differential mode. table 3.1 interface signals (cont.) bus mode 1 bus mode 2 slave type master type description (slave type, master type)
3-8 signal descriptions
symbios SYM53C710 scsi i/o processor 4-1 chapter 4 registers throughout this chapter, registers are referenced by their little endian addresses, with big endian addresses in parentheses. the term ?set? is used to refer to bits that are programmed to a binary one. similarly, the terms ?clear? and ?reset? are used to refer to bits that are programmed to a binary zero. reserved bits are designated as ?r? in each register diagram. these bits should always be written to zero; mask all information read from them. unless otherwise indicated, all bits in registers are active high, the feature is enabled by setting the bit. 4.1 register descriptions the bottom line of every register diagram shows the default register values after the chip is powered-up or reset. in the default lines below eachdiagram,avalueof1indicatesthatthebititset;avalueof0 indicates that the bit is clear; and a value of x indicates that the default is indeterminate or is a don?t care. warning : the only register that the host cpu can access while the SYM53C710 is executing scripts is the interrupt status (istat) register; attempts to access other registers will interfere with the operation of the chip. all registers are accessible using scripts.
4-2 registers table 4.1 register address map 31 16 15 0 sien sdid scntl1 scntl0 0x00 socl sodl sxfer scid 0x04 sbcl sbdl sidl sfbr 0x08 s s tat 2 s s tat 1 s s tat 0 d s tat 0 x 0 c dsa 0x10 ctest3 ctest2 ctest1 ctest0 0x14 ctest7 ctest6 ctest5 ctest4 0x18 temp 0x1c lcrc ctest8 istat dfifo 0x20 dcmd dbc 0x24 dnad 0x28 dsp 0x2c dsps 0x30 scratch 0x34 dcntl dwt dien dmode 0x38 adder 0x3c
register descriptions 4-3 register: 0x00 (0x03) scsi control zero (scntl0) read/write arb[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the SYM53C710 waits for a bus free condition to occur. 2. it asserts bsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the sel/ signal is asserted by another scsi device, the SYM53C710 deasserts bsy/, deasserts its id and sets the lost arbitration bit in the scsi status one (sstat1) register. 3. after an arbitration delay, the cpu reads the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the SYM53C710 wins arbitration. 4. once the SYM53C710 wins arbitration, sel is asserted using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 s) before a low level selection is performed. 76543210 arb[1:0] start watn epc epg aap trg 11000000 arb1 arb0 arbitration mode 0 0 simple arbitration 01 reserved 10 reserved 1 1 full arbitration, selection/reselection
4-4 registers full arbitration, selection/reselection 1. the SYM53C710 waits for a bus free condition to occur. 2. it asserts bsy/ and its scsi id (the highest priority id stored in the scsi chip id (scid) register) onto the scsi bus. 3. if the sel/ signal is asserted by another scsi device or if the SYM53C710 detects a higher priority id, the SYM53C710 deasserts bsy/, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the SYM53C710 repeats arbitration until it wins control of the scsi bus. when it wins, the won arbitration bit is set in the scsi status one (sstat1) register. 5. the SYM53C710 performs selection by asserting the following onto the scsi bus: sel/, the target?s id (storedinthe scsi destination id (sdid) register) and the SYM53C710?s id (the highest priority id stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the scsi status zero (sstat0) register. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi status zero (sstat0) register. start start sequence 5 when this bit is set, the SYM53C710 starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. do not start an arbitration sequence if the connected (con) bit in the scsi control one (scntl1) register indicates the SYM53C710 is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence is aborted, check the connected bit in the scsi control one (scntl1) register to verify that the SYM53C710 is not connected to the scsi bus.
register descriptions 4-5 watn select with atn/ on a start sequence 4 when this bit is set, the scsi atn/ signal is asserted during the selection phase (atn/ is asserted at the same time bsy/ is deasserted while selecting a target). if a selection time-out occurs while attempting to select a target device, atn/ is deasserted at the same time sel/ is deasserted. when this bit is cleared, the atn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but manual setting is possible in low level mode. epc enableparitychecking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either initiator or target mode. the host data bus is checked for odd parity if bit 2, the enable parity generation bit, is cleared. host data bus parity is checked as data is loaded into the scsi output data latch (sodl) register when sending scsi data in either initiator or target mode. if a parity error is detected, bit 0 of the scsi status zero (sstat0) register is set and an interrupt may be generated. if the SYM53C710 is operating in initiator mode and a parity error is detected, assertion of atn/ is optional, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. epg enable parity generation/parity through 2 when this bit is set, the scsi parity bit is generated by the SYM53C710. the host data bus parity lines dp[3:0] are ignored and should not be used as parity signals. when this bit is cleared, the parity present on the host data parity lines flow through the SYM53C710 internal fifos and are driven onto the scsi bus when sending data (if the host bus is set to even parity, it is changed to odd before it is sent to the scsi bus). this bit is set to enable the dp3_abrt/ pin to function as an abort input (abrt/). aap assert atn/ on parity error 1 when this bit is set, the SYM53C710 automatically asserts the scsi atn/ signal upon detection of a parity error. atn/ is only asserted in initiator mode. the atn/
4-6 registers signal is asserted before deasserting ack/ during the byte transfer with the parity error. the enable parity checking bit must also be set for the SYM53C710 to assert atn/ in this manner. the following parity errors can occur: ? a parity error detected on data received from the scsi bus. ? a parity error detected on data transferred to the SYM53C710 from the host data bus. if the assert atn/ on parity error bit is cleared or the enable parity checking bit is cleared, atn/ is not automatically asserted on the scsi bus when a parity error is received. trg target mode 0 this bit determines the default operating mode of the SYM53C710, though there are instances when the chip may act in a role other than the default. for example, a mostly initiator device may be selected as a target. an automatic mode change does not affect the state of this bit. after completion of a mode change i/o operation, the SYM53C710 returns to the role defined by this bit. when this bit is set, the chip is a target device by default. when the target mode bit is cleared, the SYM53C710 is an initiator device by default. register: 0x01 (0x02) scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi data transfer. the extra data setup time can provide additional system design flexibility, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. 76543210 exc adb esr con rst aesp snd rcv 00000000
register descriptions 4-7 adb assert scsi data bus 6 when this bit is set, the SYM53C710 drives the contents of the scsi output data latch (sodl) register onto the scsi data bus. when the SYM53C710 is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the SYM53C710 is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the sodl register can be asserted at any time, even before the SYM53C710 is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostic testing or operation in low level mode. esr enable selection and reselection 5 when this bit is set, the SYM53C710 responds to bus initiated selections and reselections. the SYM53C710 can respond to selections and reselections in both initiator and target roles. if scsi disconnect/reconnect is to be supported, set this bit as part of the initialization routine. this bit is cleared after disconnect/reselection. con connected 4 this bit is automatically set any time the SYM53C710 is connected to the scsi bus as an initiator or as a target. it is set after the SYM53C710 successfully completes arbitration or when it responds to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the SYM53C710 is not connected to the scsi bus. this bit is automatically cleared when bus free phase is detected. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature is used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the rst/ signal. the rst/ signal remains asserted until this bit is cleared. the 25 s minimum assertion time defined in the scsi specification must be timed out by the controlling microprocessor or a scripts delay routine. the rst/ signal asserts within 40 clocks and generates an interrupt if enabled in scsi interrupt enable (sien) .
4-8 registers aesp assert even scsi parity (force bad parity) 2 when this bit is set and the enable parity generation bit is set in the scsi control zero (scntl0) register, the SYM53C710 asserts even parity. it forces a scsi parity erroroneachbytesenttothescsibusfromthechip.if parity checking is enabled, then the SYM53C710 checks data received for odd parity. this bit is used for diagnostic testing and is cleared during normal operation. it is useful to generate parity errors to test error handling functions. snd start scsi send 1 setting this bit to 1 initiates a scsi send operation. bytes in the dma fifo (dfifo) are sent across the scsi bus. it is automatically set to 1 by the scripts processor to start a scsi send operation when executing scsi scripts. use it for register level programming to low level mode. rcv start scsi receive 0 setting this bit to 1 initiates a scsi receive operation. bytes are received from the scsi bus into the dma fifo (dfifo) (using the scsi fifo, if synchronous). it is automatically set to 1 by the scripts processor to start a scsi receive operation when executing scsi scripts. use it for register level programming to low level mode. register: 0x02 (0x01) scsi destination id (sdid) read/write id[7:0] scsi destination id [7:0] this register sets the scsi id of the device to be selected when a select or reselect command is executed. only one of these bits should be set for proper selection or reselection. when executing scsi scripts, the scripts processor writes the destination scsi id to this register. the scsi id is defined by the user in a scsi scripts select or reselect instruction. 7 0 id[7:0] 00000000
register descriptions 4-9 note: when using table indirect i/o commands, the destination id is loaded from the data structure. register: 0x03 (0x00) scsi interrupt enable (sien) read/write m/a initiator: phase mismatch, or target: 7 atn/ active fcmp function complete 6 sto scsi bus time-out 5 sel selected or reselected 4 sge scsi gross error 3 udc unexpected disconnect 2 rst/ scsi rst/ received 1 pa r par ity er ror 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi status zero (sstat0) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit is still set in the scsi status zero (sstat0) register. masking an interrupt does not prevent setting the istat sip bit, except in the case of nonfatal interrupts (sel and fcmp). setting a mask bit enables the assertion of irq/, for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the istat sip or dip bit is set.) the SYM53C710 irq/ output is latched. once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. masking an 76543210 m/a fcmp sto sel sge udc rst/ par 00000000
4-10 registers interrupt after the irq/ output is asserted does not cause deassertion of irq/. in the case of nonfatal interrupts, masking an interrupt after it occurs causes the istat sip bit to clear and allows pending interrupts to fall through (interrupt stacking is disabled). note: see chapter 2, ?functional description? for a more detailed description of interrupts. register: 0x04 (0x07) scsi chip id (scid) read/write id[7:0] scsi chip id [7:0] this register sets up the SYM53C710 scsi id. if more than one bit is set, the SYM53C710 responds to each corresponding scsi id. the SYM53C710 always uses the highest priority scsi id during arbitration. for example, if 0x84 is written to this register, the SYM53C710 responds when another device selects id 7 or id 2. when arbitrating for the scsi bus, use id 7 as the SYM53C710 scsi id. note:ifnobitsaresetandsimplearbitrationis performed, the SYM53C710 arbitrates as described under the scsi control zero (scntl0) section with no scsi id output onto the scsi bus. register: 0x05 (0x06) scsi transfer (sxfer) read/write note: when using table indirect i/o commands, this register is loaded from the i/o data structure. 7 0 id[7:0] 00000000 76 43 0 dhp tp[2:0] mo[3:0] 00000000
register descriptions 4-11 dhp disable halt on parity error or atn/ 7 when this bit is cleared, the SYM53C710 halts the scsi data transfer when a parity error is detected or when the atn/ signal is asserted. if atn/ or a parity error is received in the middle of a data transfer, the SYM53C710 may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the SYM53C710 transfers data until there are no outstanding synchronous offsets. if the SYM53C710 is receiving data, any data residing in the scsi or dma fifos is sent to memory before halting. when data is sent in target mode with pass parity enabled, the byte with the parity error is not sent across the scsi bus. when this bit is set, the SYM53C710 does not halt the scsi transfer when a parity error is received until the end of a block move operation. when this bit is set and the initiator asserts atn/, the SYM53C710 completes the block move and then, depending on whether or not the atn/ interrupt is enabled, either generate an interrupt or continue fetching instructions (the instruction following this is a jump address, if atn). tp[2:0] scsi synchronous transfer period [6:4] these bits determine the scsi synchronous transfer period (xferp) used by the SYM53C710 when sending synchronous scsi data in either initiator or target mode. these bits control the possible combinations and their relationship to the synchronous data transfer period used by the SYM53C710. tp2 tp1 tp0 xferp 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
4-12 registers the synchronous transfer period the SYM53C710 uses when transferring scsi data is determined in the following equations. ta bl e 4 . 2 and ta b l e 4 . 3 show examples of possible bit combinations. formula: the minimum synchronous transfer period when sending scsi data: period = tcp * (4 + xferp + 1) if bit 7 in the scsi control one (scntl1) register is set (one extra clock cycle of data setup) period = tcp * (4 + xferp) if bit 7 in the scsi control one (scntl1) register is clear (no extra clock cycle of data setup) the minimum synchronous transfer period when receiving scsi data: period = tcp * (4 + xferp) whether sending or receiving, tcp = 1 / scsi core clock frequency. the scsi core clock frequency is determined by the cf[1:0] bits in the dma control (dcntl) register and sscf[1:0] bits in scsi bus control lines (sbcl) .
register descriptions 4-13 table 4.2 examples of synchronous transfer periods and rates for scsi-1 clk (mhz) scsi clk/dcntl bits [7:6] xferp synch transfer period (ns) synch transfer rate (mbytes/s) 66.67 /3 0 180 5.55 66.67 /3 1 225 4.44 50 /2 0 160 6.25 50 /2 1 200 5 40 /2 0 200 5 37.50 /1.5 0 160 6.25 33.33 /1.5 0 180 5.55 25 /1 0 160 6.25 20 /1 0 200 5 16.67 /1 0 240 4.17 table 4.3 examples of transfer periods and rates for fast scsi-2 clk (mhz) scsi clk/sbcl bits [1:0] xferp synch transfer period (ns) synch transfer rate (mbytes/s) 66.67 /1.5 0 90 11.11 1 1. violates scsi specifications. 66.67 /1.5 1 112.5 8.88 50 /1 0 80 12.5 1 50 /1 1 100 10.0 40 /1 0 100 10.0 37.50 /1 0 106.67 9.375 33 /1 0 120 8.33 25 /1 0 160 6.25 20 /1 0 200 5 16.67 /1 0 240 4.17
4-14 registers mo[3:0] max scsi synchronous offset [3:0] these bits describe the maximum scsi synchronous offset used by the SYM53C710 when transferring synchronous scsi data in either initiator or target mode. the following table describes the possible combinations and their relationship to the synchronous data offset used by the SYM53C710. these bits determine the SYM53C710 method of transfer for data-in and data-out phases only; all other information transfers will occur asynchronously. register: 0x06 (0x05) scsi output data latch (sodl) read/write sdb[7:0] scsi output data latch [7:0] this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register is used to send data using programmed i/o. data flows through this register when sending data in any mode. it is also used to write to the synchronous data fifo when testing the chip. register: 0x07 (0x04) scsi output control latch (socl) read/write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 7 0 sdb[7:0] 00000000 76543210 req ack bsy sel atn msg c/d i/o 00000000
register descriptions 4-15 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c/d assert scsi c/d signal 1 i/o assert scsi i/o signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. scsi output control latch (socl) should only be used when transferring data using programmed i/o. some bits are set or reset when executing scsi scripts. do not write to the register once the SYM53C710 becomes connected and starts executing scsi scripts. the contents of this register are only output if the con bit in the scsi control one (scntl1) register is set. the req, bsy, sel, msg, c/d and i/o signals are only driven while in target role, and the ack and atn signals are only driven while in initiator role. register: 0x08 (0x0b) scsi first byte received (sfbr) read/write 1b[7:0] first byte received [7:0] this register contains the first byte received in any asynchronous information transfer phase. for example, when the SYM53C710 is operating in initiator mode, this register contains the first byte received in message-in, status phase, reserved in and data-in. when a block move instruction is executed for a particular phase, the first byte received is stored in this register ? even if the present phase is the same as the last phase. the first byte received value for a particular input phase is not valid until after a move instruction is executed. 7 0 1b[7:0] 00000000
4-16 registers this register is also the accumulator for register read-modify-writes with the scsi first byte received (sfbr) as the destination. this allows bit testing after an operation. additionally, the scsi first byte received (sfbr) registermaybeusedtocontainthedeviceidaftera selection or reselection, if the com bit is cleared in the dma control (dcntl) register. however, for maximum flexibility it is strongly recommended that the id byte be directed only to the longitudinal parity (lcrc) register (com bit set). the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using read/write operations. toloadthesfbrwithabytestoredinsystemmemory, the byte must first be moved to an intermediate SYM53C710 register (such as the scratch (scratch) register ), and then to the sfbr. register: 0x09 (0x0a) scsi input data latch (sidl) read only sdb[7:0] scsi input data latch [7:0] this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data receivedfromthescsibuscanbereadfromthis register. data can be written to the scsi output data latch (sodl) register and then read back into the SYM53C710 by reading this register to allow loopback testing. when receiving scsi data, the data flows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; this register contains latched data and the scsi bus data lines (sbdl) always contains exactly what is currently on the scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is not valid. 7 0 sdb[7:0] 00000000
register descriptions 4-17 register: 0x0a scsi bus data lines (sbdl) read only sdb[7:0] scsi bus data [7:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostic testing or in low level mode. register: 0x0b (0x08) scsi bus control lines (sbcl) read/write req req/ status 7 ack ack/ status 6 bsy bsy/ status 5 sel sel/ status 4 atn atn/ status 3 msg msg/ status 2 c/d c/d status 1 i/o i/o status 0 this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is 7 0 sdb[7:0] xxxxxxxx 76543210 req ack bsy sel atn msg c/d i/o xxxxxxxx
4-18 registers read. this register is used for diagnostic testing or operation in low level mode. writing to bits [7:2] has no effect. these bits determine the clock prescale factor used by the synchronous portion of the scsi core. the default is to use the same clock prescale factor as the asynchronous logic (set by cf[1:0] in dma control (dcntl) ). setting one or both of these bits allows the synchronous logic to run at a different speed than the asynchronous logic. this is necessary for fast scsi-2. refer to appendix d for more information. register: 0x0c (0x0f) dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the SYM53C710 stacks interrupts). it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dma status (dstat) and scsi status zero (sstat0) registers (in either order), insert a delay equivalent to 12 bclk periods between the reads to ensure the interrupts clear properly. also, if reading both registers when both the istat sip and dip bits may not be set, the scsi status zero (sstat0) register should be read before the dma status (dstat) register to avoid table 4.4 synchronous scsi clock control bits sscf1 sscf0 synchronous clk 0 0 set by dcntl 01sclk/1.0 10sclk/1.5 11sclk/2.0 76543210 dfe r bf abrt ssi sir wtd iid 1 0000000
register descriptions 4-19 missing a scsi interrupt. both concerns are avoided if the registers are read together as a 32-bit longword. dfe dma fifo empty 7 this status bit is set when the dma fifo (dfifo) is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. r reserved 6 bf bus fault 5 this bit is set when a host bus fault condition is detected. a host bus fault can only occur when the SYM53C710 is bus master, and is defined as a memory cycle that ends by berr/ (without halt/) or tea/ (without ta/) asserting. a bus fault occurs if retry is attempted after the first transfer of a cache line burst. arbt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs because of the following: the dp3_abrt/ input signal is asserted by another device (parity generation mode) or a software abort command is issued by setting bit 7 of the interrupt status (istat) register. ssi scripts step interrupt 3 if the single step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt is generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. wtd watchdog time-out detected 1 this status bit is set when the watchdog timer decrements to zero. the watchdog timer is only used for the host memory interface. when the timer decrements to zero, it indicates that the memory system did not assert the acknowledge signal within the specified time-out period.
4-20 registers iid illegal instruction detected 0 this status bit is set any time an illegal instruction is decoded, whether the SYM53C710 is operating in single step mode or automatically executing scsi scripts. this bit also sets if the SYM53C710 is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. note: see chapter 2, ?functional description? for a more detailed description of interrupts. register: 0x0d (0x0e) scsi status zero (sstat0) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the SYM53C710 stacks interrupts). scsi interrupt conditions are individually masked through the scsi interrupt enable (sien) register. when performing consecutive 8-bit reads of both the dma status (dstat) and scsi status zero (sstat0) registers (in either order), insert a delay equivalent to 12 clock periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the istat sip and dip bits are not set, read the scsi status zero (sstat0) register before the dma status (dstat) register to avoid missing a scsi interrupt. to clear the interrupts and avoid missing a scsi interrupt, read both registers together as a 32-bit longword. m/a initiator: phase mismatch or target: atn/ active 7 in initiator mode, this bit is set if the scsi phase asserted by the target does not match the scsi phase defined in a block move instruction. the phase is sampled when req/ is asserted by the target. in target mode, this bit is set when the atn/ signal is asserted by the initiator and the device is not in select phase. 76543210 m/a fcmp sto sel sge udc rst/ par 00000000
register descriptions 4-21 fcmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. sto scsi bus time-out 5 this bit is set if one of the following conditions occurs: ? there is a selection or reselection time-out. a selection/reselection time-out occurs if the device being selected or reselected does not respond within the 250 ms time-out period. con is not set in the interrupt status (istat) register. ? the wait for disconnect takes longer than 250 ms. the wait for disconnect instruction has a bus activity timer that is reset by the physical disconnect. ? no scsi activity occurs for 250 ms while the SYM53C710 is connected to the bus. there is a timer on all bytes (in all phases) sent or received on the scsi bus. the timer is a bus activity timer that is reset by a byte going over the scsi bus. if 250 ms pass without a byte being moved, then a time-out will occur. this interrupt can be disabled by setting bit 6 (btd) in the chip test zero (ctest0) register. the user can disable sto by setting bit 4 (notime) in the chip test seven (ctest7) register. this should be done when single stepping in the debugger. sel selected or reselected 4 this bit is set when the SYM53C710 is selected or reselected by another scsi device. the enable selection and reselection bit must be set in the scsi control one (scntl1) register for the SYM53C710 to respond to selection and reselection interrupts. sge scsi gross error 3 this bit is set when the SYM53C710 encounters a scsi gross error condition. the following conditions can cause a scsi gross error condition: ? data underflow ? reading the scsi fifo when no data is present. ? data overflow ? writing too many bytes to the scsi fifo, or the synchronous offset causes overwriting the scsi fifo.
4-22 registers ? offset underflow ? the SYM53C710 is operating in target mode and an ack/ pulse is received when the outstanding offset is zero. ? offset overflow ? the other scsi device sends a req/ or ack/ pulse with data which exceeds the maximum synchronous offset defined by the scsi transfer (sxfer) register. ? residual data in the synchronous scsi fifo ? a transfer other than synchronous data receive is started with data left in the synchronous data fifo. ? a phase change occurred with an outstanding synchronous offset when the SYM53C710 is operating as an initiator. udc unexpected disconnect 2 this bit is only valid when the SYM53C710 is in initiator mode. it is set when the SYM53C710 is operating in initiator mode and the target device unexpectedly disconnects from the scsi bus. when the SYM53C710 is executing scsi scripts, an unexpected disconnect is defined to be a disconnect that does not occur after receiving either a disconnect message (0x04) or a command complete message (0x00). for example, if an abort message is sent, the target will disconnect, resulting in a udc. when the SYM53C710 operates in low level mode, any disconnect can cause an interrupt, even a valid scsi disconnect. rst/ scsi rst/ received 1 this bit is set when the SYM53C710 detects an active rst/ signal, whether the reset is generated external to thechiporcausedbytheassertrst/bitinthe scsi control one (scntl1) register. this scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the scsi rst/ signal. pa r par ity er ror 0 this bit is set when the SYM53C710 detects a parity error while receiving or sending scsi data. the enable parity checking bit (bit 3 in the scsi control zero (scntl0) register) must be set for this bit to become active. a parity error occurs when receiving data from the
register descriptions 4-23 scsi bus or when receiving data from the host bus. from the host bus, parity is checked as it is transferred from the dma fifo to the scsi output data latch (sodl) register. a parity error occurs from the host bus only if pass through parity is enabled (bit 3 in the scsi control zero (scntl0) register = 1, bit 2 in the scsi control zero (scntl0) register = 0). note: see chapter 2, ?functional description? for a more detailed description of interrupts. register: 0x0e (0x0d) scsi status one (sstat1) read only ilf sidl register full 7 this bit is set when the sidl contains data. data is transferred from the scsi bus to the scsi input data latch (sidl) register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not flow through this register. orf sodr register full 6 this bit is set when the scsi output data register (sodr, a hidden buffer register which is not directly accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not readable or writable by the user. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl register full 5 this bit is set when the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the 76543210 ilf orf olf aip loa woa rst/ sdp/ 00000000
4-24 registers scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the SYM53C710 detects a bus free condition, asserts bsy, and asserts its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the SYM53C710 detects a bus free condition, arbitrates for the scsi bus, and loses arbitration due to another scsi device asserting the sel/ signal. woa won arbitration 2 when set, woa indicates that the SYM53C710 detects a bus free condition, arbitrates for the scsi bus and wins arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst/ scsi rst/ signal 1 this bit reports the current status of the scsi rst/ signal. this bit is not latched and changes when read. sdp/ scsi sdp/ parity signal 0 this bit represents the current status of the scsi sdp/ parity signal. this signal is not latched and changes when read.
register descriptions 4-25 register: 0x0f (0x0c) scsi status two (sstat2) read only ff[3:0] fifo flags [7:4] these four bits define the number of bytes that currently reside in the SYM53C710 scsi synchronous data fifo. these bits are not latched and they change as data moves through the fifo. because the fifo is only 8 bytes deep, values over 8 do not occur. sdp latched scsi parity 3 this bit reflects the scsi parity signal (sdp/), corresponding to the data latched in the scsi input data latch (sidl) register. it changes when a new byte is latched into the sidl register. this bit is active high, in other words, it is set when the parity signal is active. msg scsimsg/signal 2 c/d scsi c/d signal 1 i/o scsi i/o signal 0 these scsi phase status bits are latched on the asserting edge of req/ when operating in either initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in low level mode. 7 43210 ff[3:0] sdp msg c/d i/o 00000000
4-26 registers registers: 0x10?0x13 (0x10?0x13) data structure address (dsa) read/write dsa data structure address [31:0] this register contains the base address used for all table indirect calculations. it is 32 bits wide and defaults to all zeros. during any memory move operation, the contents of this register are overwritten. if the dsa value is needed for a subsequent scsi scripts, save and later restore it. note: it is possible to perform a memory-to-dsa move, but not a dsa-to-memory move. register: 0x14 (0x17) chip test zero (ctest0) read/write r reserved 7 thisbitmustalwaysbewrittentozero. btd byte-to-byte timer disable 6 this bit, in conjunction with the notime bit in ctest7, provides the following selection/byte-to-byte timer options. at power-up or if both bits are not set, the selection and byte-to-byte timer are enabled. if notime is set, both functions are disabled. if notime is not set and the byte-to-byte disable is set, the selection timer will function but the byte-to-byte timer will be disabled. grp generate receive parity for pass through 5 when this bit is set, and the SYM53C710 is in parity pass through mode, the parity received on the scsi bus will 31 0 dsa[31:0] 00000000000000000000000000000000 76543210 r btd grp ean hsc erf r ddir 000000 00
register descriptions 4-27 not pass through to the dma fifo. parity is generated as data enters the dma fifo, eliminating the possibility of bad scsi parity passing through to the host bus. a scsi parity error interrupt is generated, but a system parity problem is not created. after reset or when the bit is cleared, while pass through mode is enabled, parity received on the scsi bus will pass through the SYM53C710 unmodified. ean enableactivenegation 4 asserting this bit causes scsi request, acknowledge, data and parity to be actively deasserted, instead of relying on external pull-ups, when the SYM53C710 is driving these signals. active deassertion of these signals occurs only when the SYM53C710 is in an information transfer phase. when operating in a differential environment or at fast scsi timings, active negation should be enabled to improve setup and hold times. after reset or when the bit is cleared, active negation is disabled. hsc halt scsi clock 3 asserting this bit causes the internal divided scsi clock to a stop in a glitchless manner. this bit is used for test purposes or to lower i dd during a power-down mode. note: reinitialize scsi registers at power-up. erf extend req/ack filtering 2 the scsi core contains a special digital filter on the req/ and ack/ pins which causes glitches on deasserting edges to be disregarded. asserting this bit extends the filter delay from 30 ns to 60 ns on the deasserting edge of the req/ and ack/ signals. this 30 ns delay is used for fast scsi. note: this bit must never be set during fast scsi operations (> 5 m transfers per second), because a valid assertion is treated as a glitch. this bit does not affect transfer rates. r reserved 1 ddir data transfer direction 0 this status bit indicates which direction data is being transferred. when this bit is set, the data transfers from
4-28 registers the scsi bus to the host bus. when this bit is clear, the data transfers from the host bus to the scsi bus. this bit cannot be written. register: 0x15 (0x16) chip test one (ctest1) read only fmt[3:0] byte empty in dma fifo [7:4] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty then fmt3 will be 1. since the fmt flags indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. ffl[3:0] byte full in dma fifo [3:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 will be 1. since the ffl flags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. register: 0x16 (0x15) chip test two (ctest2) read only r reserved 7 sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status (istat) register (bit = 5). the sigp bit is used to signal a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for 7430 fmt[3:0] ffl[3:0] 11110000 76543210 rsigpsoffsfpdfpteopdreqdack 00100001
register descriptions 4-29 selection/reselection. when this register is read, the sigp bit in the interrupt status (istat) register is cleared. soff scsi offset compare 5 this bit operates differently, depending on whether the chip is an initiator or target. if the SYM53C710 is an initiator, this bit is set whenever the scsi synchronous offset counter is equal to zero. if the SYM53C710 is a target, this bit is set whenever the scsi synchronous offset counter is equal to the maximum synchronous offset defined in the scsi transfer (sxfer) register. sfp scsi fifo parity 4 this bit represents the parity bit of the scsi synchronous fifo corresponding to data read out of the fifo. reading the chip test three (ctest3) register unloads a data byte from the bottom of the scsi synchronous fifo. when the chip test three (ctest3) register is read, the data parity bit is latched into this bit location. dfp dma fifo parity 3 this bit represents the parity bit of the dma fifo when the chip test six (ctest6) register reads data out of the fifo. reading the chip test six (ctest6) register unloads one data byte from the bottom of the dma fifo. when the chip test six (ctest6) register is read the parity signal is latched into this bit location and the next byte falls down to the bottom of the fifo. teop scsi true end of process 2 this bit indicates the status of the SYM53C710 internal teop signal. the teop signal acknowledges the completion of a block move through the scsi portion of the SYM53C710. when this bit is set, teop is active. when this bit is clear, teop is inactive. dreq data request status 1 this bit indicates the status of the SYM53C710 internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive.
4-30 registers dack data acknowledge status 0 this bit indicates the status of the SYM53C710 internal data acknowledge signal (dack/). when this bit is set, dack/isinactive.whenthisbitisclear,dack/isactive. register: 0x17 (0x14) chip test three (ctest3) read only sf[7:0] scsi fifo [7:0] reading this register unloads the bottom byte of the 8-byte scsi synchronous fifo. reading this register also latches the parity bit for the fifo into the scsi fifo parity bit in the c h i p te s t tw o ( c t e s t 2 ) register. the fifo full bits in the scsi status two (sstat2) register can be read to determine how many bytes currently reside in the scsi synchronous fifo. reading this register when the scsi fifo is empty causes a scsi gross error (fifo underflow). register: 0x18 (0x1b) chip test four (ctest4) read/write mux host bus multiplex mode 7 when set, the mux bit puts the SYM53C710 into host bus mux mode. in this mode, the chip asserts a valid address for one bclk (during which as/ts is valid and the data bus is 3-stated), and then 3-states the address bus and drives the data bus (if a write). this allows the address and data buses to be tied together. it should be written prior to acquiring bus mastership. the mux mode bit allows the SYM53C710 to operate without external 7 0 sf[7:0] 00000000 765432 0 mux zmod szm slbe sfwr fbl[2:0] 00000000
register descriptions 4-31 hardware on those host buses on which data and addresses share a common 32 bits. zmod high impedance mode 6 setting this bit causes the SYM53C710 to place all output and bidirectional pins into a high impedance state. in order to read data out of the SYM53C710, this bit must be cleared. this bit is intended for board level testing only. setting this bit during system operation results in a system failure. szm scsi high impedance mode 5 setting this bit causes the SYM53C710 to place certain scsi outputs in a high impedance state. the following outputs are in a high impedance state: sd[7:0], sdp, bys/, sel/, rst/, req/, c/d, i/o, msg/, ack/, atn/. the direction control lines (sdir[7:0], sdirp, bsydir, rstdir, and seldir) are driven low and are not in a high impedance state. in order to transfer data on the scsi bus, this bit must be cleared. slbe scsi loopback enable 4 setting this bit enables loopback mode. loopback allows any scsi signal to be asserted. SYM53C710 may be an initiator or a target. it also allows the SYM53C710 to transfer data from the scsi output data latch (sodl) register back into the scsi input data latch (sidl) register. sfwr scsi fifo write enable 3 setting this bit redirects data from the sodl to the scsi fifo. a write to the scsi output data latch (sodl) register loads a byte into the scsi fifo. the parity bit loaded into the fifo is odd or even parity depending on the status of the assert scsi even parity bit in the scsi control one (scntl1) register. clearing this bit will disable this feature.
4-32 registers fbl[2:0] fifo byte control [2:0] these bits send the contents of the chip test six (ctest6) register to the appropriate byte lane of the 32-bit dma fifo. if the fbl2 bit is set, then fbl1 and fbl0 determine which of four byte lanes can be read or written. if the flb2 bit is cleared, internal logic determines which byte lane of the dma fifos is to be read or written. each of the four bytes that make up the 32-bit dma fifo can be accessed by writing these bits to the proper value. for normal operation, fbl2 must equal zero (set to this value before executing scsi scripts). register: 0x19 (0x1a) chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next data address (dnad) register. the dma next data address (dnad) register is incremented by 1, 2 or 4, based on the current dnad contents and the current dbc value. this bit automatically clears itself after incrementing the dma next data address (dnad) register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the dma byte counter (dbc) register. it is decremented fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x disabled n/a 1 0 0 0 d[7:0] 101 1 d[15:8] 1 1 0 2 d[23:16] 1 1 1 3 d[31:24] 76543210 adck bbck roff masr ddir eop dreq dack 00000000
register descriptions 4-33 by 1, 2 or 4 based on the current dbc contents and the current dnad value. this bit automatically clears itself after decrementing the dma byte counter (dbc) register. roff reset scsi offset 5 setting this bit clears any outstanding synchronous scsi req/ack offset. this bit is set when a scsi gross error condition occurs. the offset is reset when a synchronous transfer does not complete successfully. this bit automatically resets itself after clearing the synchronous offset. masr master control for set or reset pulses 4 this bit controls the operation of bits [3:0]. when this bit is set, bits [3:0] assert the corresponding signals. when this bit is reset, bits [3:0] deassert the corresponding signals. this bit and bits [3:0] should not be changed in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting the dmawr signal indicates that data is transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. eop end of process 2 setting this bit either asserts or deasserts the internal eop control signal depending on the current status of the masr bit in this register. the internal eop signal is an output from the dma portion of the SYM53C710 to the scsi portion of the SYM53C710. asserting the eop signal indicates that the last data byte has been transferred between the two portions of the chip. deasserting the eop signal indicates that the last data byte has not been transferred between the two portions of the chip. if the masr bit is configured to assert this signal, this bit automatically clears itself after pulsing the eop signal. dreq data request 1 setting this bit either asserts or deasserts the internal dreq (data request signal) depending on the current status of the masr bit in this register. asserting the
4-34 registers dreq signal indicates that the scsi portion of the SYM53C710 requests a data transfer with the dma portion of the chip. deasserting the dreq signal indicates that data should not be transferred between the scsi portion of the SYM53C710 and the dma portion. if the masr bit is configured to assert this signal, this bit automatically clears after asserting the dreq signal. dack data acknowledge 0 setting this bit either asserts or deasserts the internal dack/ data request signal dependent on the current status of the masr bit in this register. asserting the dack/ signal indicates that the dma portion of the SYM53C710 acknowledges a data transfer with the scsi portion of the chip. deasserting the dack/ signal indicates that data should not be transferred between the dma portion of the SYM53C710 and the scsi portion. if the masr bit is configured to assert this signal, this bit automatically clears itself after asserting the dack/ signal. register: 0x1a (0x19) chip test six (ctest6) read/write df[7:0] dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. when data is read from the dma fifo, the parity bit for that byte is latched and stored in the dma fifo parity bit in the c h i p te s t tw o (ctest2) register. 7 0 df[7:0] xxxxxxxx
register descriptions 4-35 to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts. note: writing to this register loads the dma fifo, regardless of the fbl bits in the chip test four (ctest4) register. use the flf bit in the chip test eight (ctest8) register to flush the dma fifo. register: 0x1b (0x18) chip test seven (ctest7) read/write cdis cache burst disable 7 when this bit is set, the SYM53C710 does not request a cachelineburst.whenthisbitisclear,thechipattempts cache line bursts when two conditions are met. the first condition is that the address must be lined up to a cache line boundary (a3?a0 must be zero). the second condition is that the transfer counter must be at least 32. cache line burst mode eliminates the need for a full handshake between the bus master and the memory device when transferring data. burst length in dmode must be 4 if caching is enabled. sc[1:0] snoop control [6:5] the sc0 and sc1 bits control the two snoop control pins. the sc1 bit controls the snoop control 1 pin all of the time. the sc0 bit controls the snoop control 0 pin only when the snoop mode bit is not set. monitoring the sc0 bit gives advance notice of a pending SYM53C710 bus request. bus snooping allows for transmission of additional information to other devices on the host bus about the current type of transfer. in bus mode 2, the host processor can snoop an alternate master read/write transfer, ensuring access to valid data. in other operating modes, these bits and pins provide additional user defined functionality. 76543210 cdis sc[1:0] notime dfp evp tt1 diff 00000000
4-36 registers notime selection time-out disable 4 setting this bit disables the 250 ms timer for all modes, including byte-to-byte. if sto is disabled, the user cannot abort a select/reselect scripts instruction using the abort bit. dfp dma fifo parity 3 this bit represents the parity bit of the dma fifo when reading data out of the dma fifo using programmed i/o. in order to transfer data to or from the dma fifo, performareadorawritetothe chip test six (ctest6) register. when loading data into the fifo using programmed i/o, write this bit to the fifo as the parity bit for each byte loaded. when writing data to the dma fifo, set this bit with the status of the parity bit to be written to the fifo before writing the byte to the fifo. evp even parity 2 parity is generated for all slave mode register reads and master mode memory writes. this bit controls the parity sense. setting this bit causes the SYM53C710 to generate even parity when driving data on the host data bus. the SYM53C710 inverts the parity bit received from the scsi bus to create even parity. in addition, the even parity received from the host bus is inverted to odd parity before the SYM53C710 checks parity and sends the data to the scsi bus. clearing this bit causes the SYM53C710 to maintain odd parity throughout the chip. tt1 transfer type bit 1 the inverted value of this bit is asserted on the tt1 pin during bus mastership in bus mode 2 only. this bit is not used in bus mode 1. diff differential mode 0 setting this bit enables the SYM53C710 to interface with external differential pair transceivers. the scsi bsy/, sel/, and rst/ are input only in differential mode. for more information on differences between the two modes, refer to the pin descriptions for these signals. resetting this bit enables se mode. this bit should be set in the initialization routine if the differential pair interface is to be used.
register descriptions 4-37 register: 0x1c (0x1c?0x1f) temporary stack (temp) read/write temp temporary stack [31:0] this 32-bit register stores the instruction address pointer for a call or a return instruction. the address pointer stored in this register is loadedintothe dma scripts pointer (dsp) register. this address points to the next instruction to be executed. do not write to temp while the SYM53C710 is executing scsi scripts. during any memory-to-memory move operation, the contents of this register are destroyed. if the temp value is needed for a subsequent scsi scripts, save and then later restore it. register: 0x20 (0x23) dma fifo (dfifo) read/write r reserved 7 bo[6:0] byte offset counter [6:0] these six bits indicate the amount of data transferred between the scsi core and the dma core. they are used to determine the number of bytes in the dma fifo when a dma error occurs. these bits are unstable while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. the following steps determine how many bytes are left in the dma fifo when an error occurs, regardless of the direction of the transfer. 31 0 temp[31:0] 00000000000000000000000000000000 76 0 r bo[6:0] 00000001
4-38 registers 1. subtract the seven least significant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. 2. and the result with 0x7f for a byte count between zero and 64. register: 0x21 (0x22) interrupt status (istat) read/write this is the only register that is accessible by the host cpu while the SYM53C710 is executing scripts (without interfering in the operation of the SYM53C710). it is used to poll for interrupts if interrupts are masked. when either the sip or dip bit is set, the dstat and sstat0 latches close and subsequent interrupts are stacked (held in a pending register ?behind? the status register). when the current interrupt is cleared by reading the appropriate status register, the stacked interrupts are transferred to the status register and cause another interrupt. when an interrupt event occurs, the SYM53C710 halts in an orderly fashion before asserting irq. if in the middle of an instruction fetch, the fetch is completed (except in the case of a bus fault or watchdog time-out), though execution does not begin. if possible, dma write operations empty the fifo before halting. all other dma operations finish only the current cycle (or burst if a cache line) before halting. scsi handshakes that have begun are completed before halting. the SYM53C710 attempts to clean up any outstanding synchronous offset. in the case of transfer control instructions, once execution begins it continues to completion before halting. if the instruction is jump/call when, the wait aborts and the dsp is updated to the transfer address before halting. all other instructions halt before completing execution. note: the istat is a shadowed register, therefore it cannot be accessed using the read/write instruction. to move the interrupt status (istat) register to the sfbr, use a memory move to transfer the istat to scratch1, then perform a scratch1-to-sfbr move. 76543210 abrt rst sigp rcon rsipdip 000 00 000
register descriptions 4-39 abrt abort operation 7 setting this bit aborts the current operation under execution by the SYM53C710. if this bit is set and an interrupt is received, reset this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the interrupt status (istat) register. 4. if the scsi interrupt pending bit is set, read the scsi status zero (sstat0) register to determine the cause ofthescsiinterruptandgobacktostep2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, write 0x00 value to this register to clear the abort. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. the abort operation aborts a sequence of instructions. it does not abort a current opcode execution. abort looks for an appropriate time to interrupt. during a selection/reselection, abort interrupts at sto. during a move, abort waits for the transfer to complete, or for the target to change phase or disconnect. rst software reset 6 setting this bit resets the SYM53C710. all registers except the dcntl ea bit are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this bit is not self-clearing; it must be cleared to remove the reset condition (a hardware reset also clears this bit). this reset does not clear the enable acknowledge (ea) bit, the function control one (fc1) bit, or the com bit in the dma control (dcntl) register. sigp signal process 5 sigp is a read/write bit that is writable at any time, and polled and reset using c h i p te s t tw o ( c t e s t 2 ) .the
4-40 registers sigp bit is used in various ways to pass a flag to or from a running scripts. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that opcode to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. note: if the sigp bit is active when a selection/reselection occurs, the autoswitching from/to target mode is disabled and must be manually set by either the host or a scripts. r reserved 4 con connected 3 this bit is automatically set any time the SYM53C710 is connected to the scsi bus as an initiator or as a target. it is set after successfully completing arbitration or when the SYM53C710 responds to a bus initiated selection or reselection. it is also set after the SYM53C710 wins arbitration when operating in low level mode. when this bit is clear, the SYM53C710 is not connected to the scsi bus. this bit is unlatched and may be changing as it is read. r reserved 2 sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the SYM53C710. the following conditions cause a scsi interrupt to occur: ? a phase mismatch (initiator mode) or atn/ becomes active (target mode) ? an arbitration sequence completes ? a selection or reselection time-out occurs ? the SYM53C710 is selected or reselected ? a scsi gross error occurs ? an unexpected disconnect occurs ? a scsi reset occurs
register descriptions 4-41 ? a parity error is detected to determine exactly which condition(s) caused the interrupt, read the scsi status zero (sstat0) register. this bit is synchronous to bclk, but may change during read cycles. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the SYM53C710. the following conditions cause a dma interrupt to occur: ? a bus fault is detected ? an abort condition is detected ? a scripts instruction is executed in single step mode ? a scripts interrupt instruction is executed ? the watchdog timer decrements to zero ? an illegal instruction is detected to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register. the bit is synchronous to bclk, but may change during read cycles. note: see chapter 2, ?functional description? for a more detailed description of interrupts. register: 0x22 (0x21) chip test eight (ctest8) read/write v[3:0] chip revision level [7:4] these bits identify the chip revision level for software purposes. this technical manual applies to devices with revision level 2 (0010). 7 43210 v[3:0] flf clf fm sm vvvv0 00 0
4-42 registers flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma next data address (dnad) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the SYM53C710. setting this bit does not flush the scsi fifo or sidl. note: all chip registers may be read during flush operations. clf clear dma and scsi fifos 2 when this bit is set, all data pointers for the scsi and dma fifos are cleared. in addition to the scsi and dma fifo pointers, the sidl, sodl, and sodr full bits in the scsi status one (sstat1) register are cleared. data in either of the fifos is lost. this bit automatically resets after the SYM53C710 successfully clears the appropriate fifo pointers and registers. fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the opcode portion of an instruction fetch. this allows scripts to be stored in a prom while data tables are stored in ram, reducing the long delay associated with arbitrating for the host bus in order to fetch scripts instructions from system memory. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. sm snoop pins mode 0 when set, the two snoop pins change functions and become pure outputs that are always driven, except when in zmode.
register descriptions 4-43 when clear, the snoop pins are driven during host bus ownership with the values of the ctest7 sc[1:0] bits. register: 0x23 (0x20) longitudinal parity (lcrc) read/write lcrc longitudinal parity [7:0] this register contains the longitudinal parity for all data crossing the dma fifo to or from the scsi core. the parity consists of an exclusive or of all data bytes. writing to this register clears its contents to 0x00 regardless of the value written. like the scsi first byte received (sfbr) register in the sym53c700, this register is used by the scsi core to hold the scsi id value during selection and reselection. the longitudinal parity (lcrc) register is used instead of the sfbr because the sfbr is used as an accumulator during many scripts operations, and may be overwritten at any time by a selection or reselection. pin function sc0 becomes a copy of the internal bus request signal. signal asserts prior to br/ and is negated during the as/ (asynchronous, or ts/, synchronous) of the last bus cycle. note: if cache line bursting is enabled, the signal is negated prior to the release of the last ta. sc1 drives the value in the sc1 register bit. 7 0 lcrc[7:0] 00000000
4-44 registers register: 0x24?0x26 (0x25?0x27) dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the SYM53C710. the dbc counter is decremented each time the as/ signal is pulsed by the SYM53C710. it is decremented by an amount equal to the number of bytes that were transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dbc register, an illegal instruction interrupt occurs if the chip is not operating in a target mode command phase. the dma byte counter (dbc) register is also used during table indirect i/o scripts to hold the offset value. register: 0x27 (0x24) dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the SYM53C710 to execute. this register has a different 23 0 dbc[23:0] 000000000000000000000000 7 0 dcmd[7:0] 00000000
register descriptions 4-45 format for each instruction. for a complete description, refer to the SYM53C710 instruction set. register: 0x28?0x2b (0x28?0x2b) dma next data address (dnad) read/write dnad dma next data address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dma scripts pointer save (dsps) register. its value may not be valid except in certain abort conditions. to maintain software compatibility with the sym53c700, interrupt vectors are read from the dma scripts pointer save (dsps) register. register: 0x2c?0x2f (0x2c?0x2f) dma scripts pointer (dsp) read/write dsp dma scripts pointer [7:0] to execute scsi scripts, the address of the first scsi scripts must be written to this register. in normal scripts operation, once the starting address of the scsi scripts is written to this register, the scripts are automatically fetched and executed until an interrupt condition occurs. in single step mode, there is a scripts step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address, but the start dma bit (bit 2), dma con- trol (dcntl) must be set each time the step interrupt 31 0 dnad[31:0] 00000000000000000000000000000000 7 0 dsp[7:0] 00000000
4-46 registers occurs to fetch and execute the next scsi scripts. when writing this register eight bits at a time, writing the upper eight bits, 2f (2c), begins execution of scsi = scripts. register: 0x30?0x33 (0x30?0x33) dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [7:0] this register contains the second longword of read/write or transfer control scripts instructions. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is fetched, this register holds the interrupt vector. register: 0x34?0x37 (0x34?0x37) scratch (scratch) read/write scratch scratch (scratch) [7:0] this is a general purpose, user-definable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch (scratch) register alter its contents. the scratch (scratch) register combined with register-to-register move, and, or, and add operations provides the capability to write a complete scsi interface program in scripts. 7 0 dsps[7:0] 00000000 7 0 scratch[7:0] 00000000
register descriptions 4-47 register: 0x38 (0x3b) dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the number of cycles performed per bus ownership. the SYM53C710 asserts the bus request output when the dma fifo can accommodate a transfer of at least one burst size of data. bus request is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even though less than a full burst of transfers may be performed. to perform cache line burst, these bits must be set to 4 transfers and cache bursting must be enabled (ctest7). the SYM53C710 inserts a ?fairness delay? of approximately 5 to 8 bclks between bus ownerships. this gives the cpu and other bus master devices the opportunity to access memory between bursts. fc[1:0] function code [5:4] these bits are user defined. their values are asserted onto the corresponding device pins during bus mastership. these bits/pins are active in both bus modes. pd program/data 3 this bit affects the function of the fc0/ pin. setting this bit causes the SYM53C710 to drive the fc0/ signal low when fetching instructions from memory. clearing this bit causes the SYM53C710 to drive the fc0/ signal high when fetching instructions from memory. 76543210 bl[1:0] fc[1:0] pd fam u0 man 00000000 bl1 bl0 burst length 0 0 1 - transfer burst 0 1 2 - transfer burst 1 0 4 - transfer burst 1 1 8 - transfer burst
4-48 registers thefc0/signalisalwaysdrivenhighwhenmovingdata to or from memory and can only be driven low during instruction fetch cycles. this feature can be used to allow scripts and data to be stored in separate memory banks. fam fixed address mode 2 when the fixed address mode bit is set, the address pointer in the dma next data address (dnad) register is disabled and will not increment after each data transfer. if this bit is clear, the pointer increments after each data transfer. the fixed address mode feature is used to transfer data to or from a fixed port address. this port width must be 32 bits and longword aligned. setting this bit does not affect scripts fetching instructions; only data transfer instructions are affected. u0 user programmable transfer type 1 in both bus modes, upso-tt0/ is a general purpose output pin. the value of this bit is asserted onto the upso-tt0/ pin while the SYM53C710 is a bus master, to indicate the type of access for the current bus transfer. man manual start mode 0 clearing this bit causes the SYM53C710 to automatically fetch and execute scsi scripts after the dma scripts pointer (dsp) register is written. setting this bit disables the SYM53C710 from automatically fetching and executing scsi scripts after the dma scripts pointer (dsp) register is written. when the start dma bit in the dma control (dcntl) register is cleared, it controls the start time of the operation. once the start dma bit in the dma control (dcntl) is set, the SYM53C710 automatically fetches and executes each instruction.
register descriptions 4-49 register: 0x39 (0x3a) dma interrupt enable (dien) read/write r reserved [7:6] bf bus fault 5 abrt abort operation 4 ssi scsi set interrupt 3 sir scripts interrupt instruction received 2 wtd watchdog time-out detected 1 iid illegal instruction detected 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit is still set in the dma status (dstat) register. masking an interrupt does not prevent setting the istat dip from being set; all dma interrupts are considered fatal. setting a mask bit enables the assertion of irq/ for the corresponding interrupt. a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through. interrupt stacking does not begin until either the istat sip or dip bit is set. the SYM53C710 irq/ output is latched; once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is asserted does not cause irq/ to be deasserted. note: see chapter 2, ?functional description? for a more detailed description of interrupts. 76543210 r bf abrt ssi sir wtd iid 0 0000000
4-50 registers register: 0x3a (0x39) dma watchdog timer (dwt) read/write dwt dma watchdog timer [7:0] the dma watchdog timer register provides a time-out mechanism during data transfers between the SYM53C710 and memory. this register determines the amount of time that the SYM53C710 waits for the assertion of the transfer acknowledge (ta/) signal after starting a bus cycle. write the time-out value to this register during initialization. every time that the SYM53C710 transfers data to/from memory, the value stored in this register is loaded into the counter. disable the time-out feature by writing 0x00 to this register. the unit time base for this register is 16 * bclk input period. for example, at 50 mhz the time base for this register is 16 x 20 ns = 320 ns. if a time-out of 50 sis desired, then this register should be loaded with a value of 0x9d. the minimum time-out value that should be loaded into this register is 0x02; the value 0x01 does not provide a reliable time-out period. 7 0 dwt[7:0] 00000000
register descriptions 4-51 register: 0x3b (0x38) dma control (dcntl) read/write cf[1:0] clock frequency [7:6] these two bits determine the sclk prescale factor used by the SYM53C710 scsi core; the internal scsi clock is derived from the externally applied sclk. the above table describes how to program these two bits. note: it is important that these bits be set to the proper values to guarantee that the SYM53C710 meets the scsi timings as defined by the ansi specification. these bits affect both asynchronous and synchronous timings (unless the synchronous clock is decoupled using the scsi bus con- trol lines (sbcl) register). ea enable ack 5 setting this bit causes the sterm/_ta/ pin to become bidirectional. as a result, the SYM53C710 generates sterm/_ta/ during slave accesses. when this bit is clear, the SYM53C710 will monitor sterm/_ta/ to determine the end of a cycle. this bit takes effect during the cycle in which it is set; setting this bit must be the first i/o performed to the SYM53C710 if this feature is desired. see chapter 2, ?functional description? for information on bidirectional sterm/_ta/. ssm single step mode 4 setting this bit causes the SYM53C710 to stop after executing each scripts instruction, and generate a 76543210 cf[1:0] ea ssm llm std fa com 00000000 cf1 cf0 scsi core clock sclk frequency 1 1 sclk/3 50.01 ? 66.67 mhz 0 0 sclk 237.51 ? 50.00 mhz 0 1 sclk 1.525.01 ? 37.50 mhz 1 0 sclk 116.67 ? 25.00 mhz
4-52 registers scripts step interrupt. when this bit is cleared, the SYM53C710 does not stop after each instruction. it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit cleared. to restart the SYM53C710 after it generates a scripts step interrupt, the interrupt status (istat) and dma status (dstat) registers should be read to clear the interrupt and then the start dma bit in this register should be set. llm enable scsi low level mode 3 setting this bit places the SYM53C710 in low level mode. in this mode, no dma operations can occur, and no scripts instructions can be executed. arbitration and selection are performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in scsi scripts mode. std start dma operation 2 the SYM53C710 fetches a scsi scripts instruction from the address contained in the dma scripts pointer (dsp) register when this bit is set. this bit is required if the SYM53C710 is in one of the following modes: ? manualstartmode?bit0inthe dma mode (dmode) register is set ? singlestepmode?bit4inthe dma control (dcntl) is set when the SYM53C710 is executing scripts in manual start mode, the start dma bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. when the SYM53C710 is in single step mode, set the start dma bit to restart execution of scripts after a single step interrupt. fa fast arbitration 1 when this bit is set, the SYM53C710 immediately becomes bus master after receiving a bus grant, saving one clock cycle of arbitration time. when this bit is clear, the SYM53C710 follows the normal arbitration sequence.
register descriptions 4-53 com sym53c700 compatibility 0 when this bit is clear, the SYM53C710 behaves in a manner compatible with the sym53c700; selection/reselection ids are stored in both the longitudinal parity (lcrc) and scsi first byte received (sfbr) registers, and autoswitching is enabled. the default condition of this bit (clear) causes the SYM53C710 to act the same as the sym53c700. when this bit is set, the id is stored only in the longitudinal parity (lcrc) register, protecting the sfbr from being overwritten if a selection/reselection occurs during dma register-to-register operation. when this bit is set, autoswitching is disabled. register: 0x3c?0x3f (0x3c?0x3f) adder sum output (adder) read only adder adder sum output [31:0] this 32-bit register contains the output of the internal adder, and is used primarily for test purposes. 31 0 adder[31:0] 00000000000000000000000000000000
4-54 registers
symbios SYM53C710 scsi i/o processor 5-1 chapter 5 instruction set of the i/o processor this chapter contains the following sections: ? section 5.1, ?getting started? ? section 5.2, ?i/o instructions? ? section 5.3, ?read/write instructions? ? section 5.4, ?transfer control instructions? ? section 5.5, ?memory move instructions? after power-up and initialization of the SYM53C710, the chip may be operated in one of two modes: 1. low level register interface 2. scsi scripts mode in the low level register interface, the user has access to the dma control logic and the scsi bus control logic. the chip may be operated much like a sym53c80. an external processor has access to the scsi bus signals and the low level dma signals, to allow creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chip?s pins. to operate in the scsi scripts mode, the SYM53C710 requires only a scripts start address. all commands are fetched from external memory. the SYM53C710 fetches and executes its own instructions by becoming a bus master on the host bus and fetching two or three 32-bit words into its registers. commands are fetched until an interrupt command is encountered, or until an unexpected event (such as
5-2 instruction set of the i/o processor detection of a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the SYM53C710 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer (dsp) register to restart the automatic fetch and execution of instructions. the scsi scripts mode of execution allows the SYM53C710 to make decisions based on the status of the scsi bus. this reduces the need for interrupt service by the microprocessor. given the rich set of scsi-oriented features included in the command set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery should never be required. five types of instructions are implemented in the SYM53C710: ? block move ? i/o ? read/write ? transfer control ? memory move each instruction consists of two or three 32-bit words. the first 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary stack (temp) register.
getting started 5-3 5.1 getting started before fetching and executing scripts, initialize the SYM53C710 registers. if using the bidirectional sterm/_ta/ feature, initialize the ea bit in the dma control (dcntl) before any other registers. also, at a minimum, the dma registers ( dma mode (dmode) , dma control (dcntl) ,and dma interrupt enable (dien) and scsi registers scsi control zero (scntl0) , scsi control one (scntl1) , scsi transfer (sxfer) , scsi interrupt enable (sien) ,and scsi bus control lines (sbcl) should be initialized to their desired values, if the default values are not correct. after these registers are initialized, the starting address of scripts instructions is loaded into the dsp. when the high byte of dsp is written, the scripts begin executing.
5-4 instruction set of the i/o processor figure 5.1 describes the block move instruction register. figure 5.1 block move instruction register 31 30 29282726252423222120191817161514131211109876543210 31 30 29282726252423222120191817161514131211109876543210 dsps register dcmd register dbc register 24-bit block move byte counter i/o c/d msg/ opcode table indirect addressing indirect addressing (sym53c700 compatible) 0 0
getting started 5-5 instruction type block move [31:30] indirect addressing 29 when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chip?s address register and incremented as data is transferred. when set, the 32-bit data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chip?s dma next data address (dnad) register using a third longword fetch (4-byte transfer across the host computer bus). direct addressing the byte count and absolute address are: indirect addressing use the byte count and fetch the data address from the address in the command. the byte count is contained in the dma byte counter (dbc) register and the data address is fetched from the dma scripts pointer save (dsps) register. once the data buffer is loaded, it is executed as if the chip were operating in the direct mode. table indirect 28 when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/destination address are fetched from this address. use the signed integer offset in bits [23:0] of the second 4 bytes of the instruction to fetch first the byte count and command byte count address of data command byte count address of pointer to data
5-6 instruction set of the i/o processor then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign extended values of all ones for negative values are allowed, but ignored. priortothestartofani/o,the data structure address (dsa) register must be loaded with the base address of the i/o data structure. the address may be any longword on a longword boundary. at the start of an i/o, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from this address brings the data values into the chip. for a move command, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the SYM53C710. execution begins at this point. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and can cross system segment boundaries. there are two restrictions on the placement of data in system memory. the eight bytes of data in the move command must be contiguous, as shown below. indirect data fetches are not available during execution of a memory-to-memory dma operation. opcode 27 this 1-bit opcode field defines the instruction to be executed. the opcode field bit has different meaning depending on whether the SYM53C710 is operating in initiator or target mode. entering a reserved value for the command not used xx table offset 00 byte count physical data address
getting started 5-7 current operating mode causes an illegal instruction interrupt. target mode in target mode, the opcode bit defines the following operations: these instructions perform the following steps: 1. the SYM53C710 verifies that it is connected to the scsi bus as a target before executing this instruction. 2. the SYM53C710 asserts the scsi phase signals (msg/, c/d, and i/o) as defined by the phase field bits in the instruction. 3. if the instruction is for the command phase, the SYM53C710 receives the first command byte and decodes its scsi group code. a) if the scsi group code is either group 0, group 1, group 2, or group 5, then the SYM53C710 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. b) if any other group code is received, the dma byte counter (dbc) register is not modified and the SYM53C710 requests the number of bytes specified in the dma byte counter (dbc) register. if the dma byte counter (dbc) register contains 0x000000, an illegal instruction interrupt is generated. 4. the SYM53C710 transfers the number of bytes specified in the dma byte counter (dbc) register starting at the address specified in the dma next data address (dnad) register. 5. if the scsi atn/ signal is asserted by the initiator or if a parity error occurs during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error atn bit in the scsi transfer opc instruction defined 0move 1 reserved
5-8 instruction set of the i/o processor (sxfer) register controls whether an interrupt is generated. initiator mode in target mode, the opcode bit defines the following operations: these instructions perform the following steps: 1. the SYM53C710 verifies that it is connected to the scsi bus as an initiator before executing this instruction. 2. the SYM53C710 waits for an unserviced phase to occur. an unserviced phase is defined as any phase (with req/ asserted) for which the SYM53C710 has not yet transferred data by responding with an ack/. 3. the SYM53C710 compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status two (sstat2) register. these phase lines are latched when req/ is asserted. 4. if the scsi phase bits match the value stored in the scsi status two (sstat2) register, the SYM53C710 transfers the number of bytes specified in the dma byte counter (dbc) register starting at the address pointed to by the dma next data address (dnad) register. 5. if the scsi phase bits do not match the value stored in the scsi status two (sstat2) register, the SYM53C710 generates a phase mismatch interrupt and the command is not executed. scsi phase [26:24] this 3-bit field defines the desired scsi information transfer phase. when the SYM53C710 operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status two (sstat2) register. when the SYM53C710 operates in target mode, the sym53710 asserts the phase defined in this field. opc instruction defined 0chmov 1move
getting started 5-9 the following table describes the possible combinations and the corresponding scsi phase. transfer counter [23:0] this 24-bit field specifies the number of data bytes to be moved between the SYM53C710 and system memory. the field is stored in the dma byte counter (dbc) register. when the SYM53C710 transfers data to or from memory, the dma byte counter (dbc) register is decremented by the number of bytes transferred. in addition, the dma next data address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dma byte counter (dbc) register has been decremented to zero. at that time, the SYM53C710 fetches the next instruction. start address [31:0] this 32-bit field specifies the starting address of the data to be moved to or from memory. this field is copied to the dma next data address (dnad) register. when the SYM53C710 transfers data to or from memory, the dma next data address (dnad) register is incremented by the number of bytes transferred. table 5.1 scsi information transfer phase msg c_d i_o scsi phase 00 0data-out 00 1data-in 0 1 0 command 01 1status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in
5-10 instruction set of the i/o processor 5.2 i/o instructions figure 5.2 describes the i/o instruction register. figure 5.2 i/o instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register r rr r set/clear atn/ set/clear ack/ set/clear target mode set/clear carry scsi id 0 scsi id 1 scsi id 2 scsi id 3 scsi id 4 scsi id 5 scsi id 6 scsi id 7 select with atn table indirect addressing relative addressing opcode bit 0 opcode bit 1 opcode bit 2 1 0
i/o instructions 5-11 instruction type - i/o instruction [31:30] opcode [29:27] the opcode bits have different meanings, depending on whether the SYM53C710 is operating in initiator or target mode. opcode values 101 through 111 are not reserved, but are considered read/write instructions rather than i/o, and are discussed in the read/write instructions section. target mode reselect instruction 1. the SYM53C710 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if the SYM53C710 loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the SYM53C710 wins arbitration, it attempts to reselect the scsi device whose id is defined in the destination id field of the instruction. once the SYM53C710 has won arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 3. if the SYM53C710 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next data address (dnad) register. the SYM53C710 automatically configures itself to be in the initiator mode if it is reselected, or the target mode if it is selected, provided the sym53c700 compatibility bit (bit 0 in the dma control (dcntl) is set. for more information, please refer to the section 2.7.2, ?select/reselect during opc2 opc1 opc0 instruction defined 0 0 0 reselect 0 0 1 disconnect 010waitselect 011set 100clear
5-12 instruction set of the i/o processor selection/reselection? of chapter 2, ?functional description? . disconnect instruction the SYM53C710 disconnects from the scsi bus by deasserting all scsi signal outputs. the scsi direction control signals are deasserted, which disables the differential pair output drivers. wait select instruction 1. if the SYM53C710 is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 2. if reselected, the SYM53C710 fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next data address (dnad) register. the SYM53C710 automatically configures into initiator mode when reselected, provided the sym53c700 compatibility bit (bit 0 in the dma control (dcntl) register) is set. for more information, please refer to the section 2.7.2, ?select/reselect during selection/reselection? of chapter 2, ?functional description? . 3. if the cpu sets the sigp bit in the interrupt status (istat) register, the SYM53C710 will abort the wait select instruction and fetch the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next data address (dnad) register. set instruction when the ack/ or atn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. ack/ should not be set except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. note: none of the signals are affected on the scsi bus in target mode.
i/o instructions 5-13 clear instruction when the ack/ or atn/ bits are set, the corresponding bits are cleared in the scsi output control latch (socl) register. atn/ should not be cleared except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is also cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are affected on the scsi bus in target mode. initiator mode select instruction 1. the SYM53C710 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if the SYM53C710 loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the SYM53C710 wins arbitration, it attempts to select the scsi device whose id is defined in the destination id field of the instruction. it then fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 3. if the SYM53C710 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next data address (dnad) register. the SYM53C710 automatically configures itself to initiator mode if it is reselected, or to target mode if it is selected, provided the sym53c700 compatibility bit (bit 0 in the dma control (dcntl) ) is set. for more information, opc2 opc1 opc0 instruction defined 0 0 0 reselect 0 0 1 wait disconnect 0 1 0 wait reselect 011set 100clear
5-14 instruction set of the i/o processor please refer to the section 2.7.2, ?select/reselect during selection/reselection? of chapter 2, ?functional description? . 4. if the select with atn/ field is set, the atn/ signal is asserted during the selection phase. wait reselect instruction the SYM53C710 waits for the target to perform a ?legal? disconnect from the scsi bus. a ?legal? disconnect occurs when bsy/ and sel/ are inactive for a minimum of one bus free delay (400 ns), after the SYM53C710 has received a disconnect message or a command complete message. wait reselect instruction 1. if the SYM53C710 is selected before being reselected, it fetches the next instruction from the address pointed to bythe32-bitjumpaddressfieldstoredinthe dma next data address (dnad) register. the SYM53C710 automatically configures itself to be in target mode when selected, provided the sym53c700 compatibility bit (bit 0 in the dma control (dcntl) )isset.formore information, please refer to the section 2.7.2, ?select/reselect during selection/reselection? of chapter 2, ?functional description? . 2. if the SYM53C710 is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 3. if the cpu sets the sigp bit in the interrupt status (istat) register, the SYM53C710 aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next data address (dnad) register. set instruction when the ack/ or atn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. ack/ should not be set except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when
i/o instructions 5-15 the carry bit is set, the corresponding bit in the alu is set. clear instruction when the ack/ or atn/ bits are set, the corresponding bits are cleared in the scsi output control latch (socl) register. atn/ should not be cleared except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next data address (dnad) register is used as a relative displacement from the current dsp address. this bit should only be used in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is used as an offset relative to the value in the data structure address (dsa) register. the scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, the dsa must be loaded with the base address of the i/o data structure. the address may be any longword on a longword boundary. at the start of an i/o, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from the address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and can cross system segment boundaries. there are two restrictions on the placement of data in system memory.
5-16 instruction set of the i/o processor ? the i/o data structure must lie within the 8 mbyte above or below the base address. ? an i/o command structure must have all four bytes contiguous in system memory, as shown below. the dhp/period/offset bits are ordered as in the scsi transfer (sxfer) register. this bit should only be used in conjunction with the select, reselect, wait select, and wait reselect instructions. bits 25 or 26 may be set individually or in combination. direct uses the device id and physical address in the command. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the command, but treats the alternate address as a relative jump. 00 id dh/period/offset 00 bit 25 bit 26 addressing mode 00direct 0 1 table indirect 10relative 11tablerelative command id not used not used absolute alternate address command table offset absolute alternate address
i/o instructions 5-17 table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. adds the value in bits [23:0] of the first four bytes of the scripts to the data structure base address to form the fetch address. select with atn/ 24 this bit specifies whether atn/ will be asserted during the selection phase when the SYM53C710 is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. scsi destination id [23:16] this 8-bit field specifies the destination scsi id for an i/o instruction. only one bit may be set in this field. set/clear carry 10 this bit is used in conjunction with a set or clear command to set or clear the carry bit. setting this bit with a set command asserts the carry bit in the alu. clearing this bit with a set command deasserts the carry bit in the alu. set/clear target mode 9 this bit is used in conjunction with a set or clear command to set or clear target mode. setting this bit with a set command configures the SYM53C710 as a target device (this sets bit 0 of the scsi control zero (scntl0) register). setting this bit with a clear command configures the SYM53C710 as an initiator device (this clears bit 0 of the scsi control zero (scntl0) register). command id not used not used xx alternate jump offset command table offset xx alternate jump offset
5-18 instruction set of the i/o processor set/clear ack/ 6 set/clear atn/ 3 these two bits are used in conjunction with a set or clear command to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi ack/ signal, bit 3 controls the scsi atn/ signal. setting either of these bits sets or resets the corresponding bit in the scsi output control latch (socl) register, depending on the command used. the set command is used to assert ack/ and/or atn/ on the scsi bus. the clear command is used to deassert ack/ and/or atn/ on the scsi bus. since ack/ and atn/ are initiator signals, they are not asserted on the scsi bus unless the SYM53C710 is operating as an initiator or the scsi loopback enable bit is set in the chip test four (ctest4) register. the set/clear scsi ack/atn instruction is used after message phase block move operations, to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, an assert scsi atn instruction would be issued before a clear scsi ack instruction. reserved [2:0] jump address [31:0] this 32-bit field specifies the address of the instruction to fetch when the SYM53C710 encounters a jump condition. the SYM53C710 fetches instructions from the address pointed to by this field whenever the SYM53C710 encounters a scsi condition that is different from the condition specified in the instruction. for example, during the execution of a select instruction in initiator mode, if the SYM53C710 is reselected, then the next instruction is fetched from the address pointed to by the jump address field. for a complete description of the different jump conditions, refer to the description of each instruction.
read/write instructions 5-19 5.3 read/write instructions figure 5.3 describes the read/write instruction register. figure 5.3 read/write instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register a0 a1 a2 a3 a4 a5 0 (reserved) 0 (reserved) carry enable operator 0 operator 1 opcode bit 0 opcode bit 1 opcode bit 2 1 0 immediate data reserved (must be 0) register address
5-20 instruction set of the i/o processor instruction type - read/write instruction [31:30] opcode [29:27] the combinations of these bits determine if the instruction is a read/write or i/o instruction. opcodes 000 through 100 are considered i/o instructions. operator [26:25] carry enable 24 when this bit is set, it allows the previous carry value to be used by the present add instruction. the carry value remainsintactunlessitismodifiedbyanadd,setcarry or clear carry instruction. all other instructions do not affect carry. if carry enable is not set, no carry is used during the present add instruction. register address - a[5:0] [21:16] register values may be changed from scripts in read-modify-write cycles or move to/from sfbr cycles. a[5:0] select an 8-bit source/destination register within the SYM53C710. register addresses are always written usinglittleendianbyteorientation. table 5.2 read/write instructions operator bits [26:25] opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr 00 immediate data to destination register immediate data to scsi first byte received (sfbr) immediate data to destination register 01 immediate data or?ed with destination register immediate data or register to scsi first byte received (sfbr) immediate data or?ed with scsi first byte received (sfbr) to destination register 10 immediate data and?ed with destination register immediate data and register to scsi first byte received (sfbr) immediate data and?ed with scsi first byte received (sfbr) to destination register 11 immediate data added to destination register immediate data added with register to scsi first byte received (sfbr) immediatedataaddedwith scsi first byte received (sfbr) to destination register
read/write instructions 5-21 5.3.1 read-modify-write cycles in this cycle, the register is read, the selected operation is performed, and the result is written back to the source register. the add operation can be used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. 5.3.2 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the scsi first byte received (sfbr) . the possible functions of this command are: ? write one byte (value contained within the scripts instruction) into any chip register. ? move to/from the scsi first byte received (sfbr) from/to any other register. ? alter the value of a register with and/or/add operators. ? after moving values to the sfbr, the compare and jump, call, or similar commands may be used to check the value. ? amovetosfbrfollowedbyamovefromsfbrcanbeusedto perform a register to register move. note: because the interrupt status (istat) register is a shadowed register, it cannot be accessed using the read/write instruction. to move the interrupt status (istat) register to the sfbr, use a memory move to transfer the istat to scratch1, then perform a scratchtosfbrmove.
5-22 instruction set of the i/o processor 5.4 transfer control instructions figure 5.4 describes the transfer control instruction register. figure 5.4 transfer control instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register wait for valid phase compare phase compare data jump if: true=1, false=0 0 (reserved) carry test 0 (reserved) relative addressing mode i/o c/d msg opcode bit 0 opcode bit 1 opcode bit 2 1 0 mask for compare data to be compared with the scsi first byte received
transfer control instructions 5-23 instruction type - [31:30] transfer control instruction opcode [29:27] this 3-bit field specifies the type of transfer control instructions to be executed. all transfer control instructions can be dependent on a comparison of the scsi information transfer phase with the phase field, and/or a comparison of the first byte received with the data compare field. each instruction can operate in initiator or target mode. jump instruction the SYM53C710 compares the phase and/or data as defined by the phase compare, data compare and true/false bit fields. if the comparisons are true, the SYM53C710 loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. the dma scripts pointer (dsp) register now contains the address of the next instruction. if the comparisons are false, the SYM53C710 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. call instruction the SYM53C710 compares the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, the SYM53C710 loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. table 5.3 transfer control instructions opc2 opc1 opc0 instruction defined 000jump 001call 010return 0 1 1 interrupt 1 x x reserved
5-24 instruction set of the i/o processor when the SYM53C710 executes a call instruction, the instruction pointer contained in the dma scripts pointer (dsp) register is stored in the temporary stack (temp) register. when a return instruction is executed, the value stored in the temporary stack (temp) register is returned to the dma scripts pointer (dsp) register. if the comparisons are false, the SYM53C710 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modified. note: the memory move instruction destroys the return address stored in the temporary stack (temp) register. return instruction the SYM53C710 compares the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, then the SYM53C710 loads the dma scripts pointer (dsp) register with the contents of the temporary stack (temp) register. that address value becomes the address of the next instruction. when the SYM53C710 executes a call instruction, the current instruction pointer contained in the dma scripts pointer (dsp) register is stored in the te m p o - rary stack (temp) register. when a return instruction is executed, the value stored in the temporary stack (temp) register is returned to the dma scripts pointer (dsp) register. the SYM53C710 does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, then the SYM53C710 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modified. note: the memory move instruction destroys the return address stored in the temporary stack (temp) register.
transfer control instructions 5-25 interrupt instruction the SYM53C710 compares the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, then the SYM53C710 generates an interrupt by asserting the irq/ signal. the 32-bit address field stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the isr to quickly identify the point at which the interrupt occurred. the SYM53C710 halts and the dma scripts pointer (dsp) register must be written to start any further operation. scsi phase [26:24] this 3-bit field corresponds to the three scsi bus phase signals which are compared with the phase lines latched when req/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible combinations and their corresponding scsi phase. these bits are only valid when the SYM53C710 is operating in initiator mode. when the SYM53C710 is operating in the target mode, these bits should be cleared. table 5.4 scsi phase comparisons msg c/d i/o scsi phase 000data-out 001data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in
5-26 instruction set of the i/o processor relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dsp address (which is pointing to the next instruction, not the one currently executing). relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the scripts routine currently being executed by the SYM53C710. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2?s complement), the jump can be forward or backward. a relative transfer can be made to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a scripts is written using only relative transfers it would not require any run time alteration of physical addresses, and could be stored in and executed from a prom. command condition codes absolute alternate address command condition codes xx alternate jump offset
transfer control instructions 5-27 reserved 22 carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. reserved 20 jump if true/false 19 this bit determines whether the SYM53C710 should branch when a comparison is true or when a comparison is false. this bit applies to both phase compares and data compares. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be falsetobranchonafalsecondition. compare data 18 when this bit is set, then the first byte received from the scsi data bus (contained in scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare will occur. the jump if true/false bit determines the condition (true or false) to branch on. compare phase 17 when the SYM53C710 is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by req/) are compared to the phase field in the transfer control instruction. if they match, then the comparison is true. the wait for valid phase bit controls when the compare will occur. when the SYM53C710 is operating in target mode this bit, when set, tests for an active scsi atn/ signal. bit 19 result of compare action 0 false jump taken 0truenojump 1falsenojump 1 true jump taken
5-28 instruction set of the i/o processor wait for valid phase 16 if the wait for valid phase bit is set, then the SYM53C710 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is clear, then the SYM53C710 compares the scsi phase and data immediately. data compare mask [15:8] the data compare mask allows a scripts to test certain bits within a data byte. during the data compare, any mask bits that are set cause the corresponding bit in thesfbrdatabytetobeignored. for instance, a mask of 01111111b and data compare value of 1xxxxxxxb allows the scripts processor to determine whether or not the high order bit is on while ignoring the remaining bits. data compare value [7:0] this 8-bit field is the data to be compared against the scsi first byte received (sfbr) register. these bits are used in conjunction with the data compare mask field to test for a particular data value. jump address [31:0] this 32-bit field contains the address of the next instruction to fetch when a jump is taken. once the SYM53C710 has fetched the instruction from the address pointed to by these 32 bits, this address is incremented by four, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer.
memory move instructions 5-29 5.5 memory move instructions figure 5.5 describes the memory move instruction register. figure 5.5 memory move instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29282726252423222120191817161514131211109876543210 dsps register dcmd register dbc register 24-bit memory move byte counter 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 1 1 31 30 29282726252423222120191817161514131211109876543210 temp register
5-30 instruction set of the i/o processor the memory move instruction is used to copy the specified number of bytes from the source address to the destination address. allowing the SYM53C710 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than current dma controllers. up to 16 mbytes may be transferred with one instruction. there are three restrictions: ? both the source and destination addresses must start with the same address alignment (a[1:0] must be the same). if source and destination are not aligned, then an illegal instruction interrupt will occur. if cache line bursting is enabled, address lines a[3:0] must be the same. ? during execution of this opcode, temp and dsa are destroyed. therefore, if the contents of either register are required for additional scripts, save them before any memory move is executed. before resuming a scsi scripts, restore the contents of the appropriate register. ? indirect addresses are not allowed. the memory-to-memory move instruction passes the source and destination addresses and the byte count to the SYM53C710. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another scripts is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. instruction type - memory move instruction [31:30] reserved [29:24] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt will occur. transfer count [23:0] the number of bytes to be transferred is stored in the lower 24 bits of the first instruction word.
memory move instructions 5-31 5.5.1 read/write system memory from scripts by using the memory move instruction, single or multiple register values may be transferred to or from system memory. because the chip select (cs/) input is derived from an address decode, it could activate during a memory move operation if the source/destination address decodes to within the chip?s register space. if this occurs, the register indicated by the lower 6 bits of the memory address is taken to be the data source or destination. in this way, register values can be saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the sfbr is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. toloadthesfbrwithabytestoredinsystemmemory,thebytemust first be moved to an intermediate SYM53C710 register (for example, the scratch (scratch) ), and then to the sfbr. the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. note: dsa can be the destination register of a memory-to-memory transfer, but not the source.
5-32 instruction set of the i/o processor
symbios SYM53C710 scsi i/o processor 6-1 chapter 6 electrical specifications this chapter contains the following sections: ? section 6.1, ?dc characteristics? ? section 6.2, ?symbios tolerant specifications? ? section 6.3, ?ac specifications? ? section 6.4, ?bus mode 1 slave cycle? ? section 6.5, ?host bus arbitration? ? section 6.6, ?bus mode 1 fast arbitration? ? section 6.7, ?bus mode 1 bus master cycle? ? section 6.8, ?bus mode 2 slave cycle? ? section 6.9, ?host bus arbitration? ? section 6.10, ?bus mode 2 fast arbitration? ? section 6.11, ?bus mode 2 bus master cycle? ? section 6.12, ?bus mode 2 mux mode operation? 6.1 dc characteristics this section of the manual describes the SYM53C710 dc characteristics. ta b l e 6 . 1 through ta b l e 6 . 1 0 give current and voltage specifications.
6-2 electrical specifications table 6.1 absolute maximum stress ratings 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or at any other conditions beyond those indicatedinthe operating conditions section of this specification is not implied. symbol parameter min max units t stg storage temperature ? 55 150 c v dd supply voltage ? 0.5 7.0 v v in input voltage v ss ? 0.5 v dd +0.5 v i lu latch-up current ? 2vSYM53C710 ? 50 ma i dd supply current (dynamic) - SYM53C710-1 ? 60 ma t a operating temperature (free air) 0 70 c ja thermal resistance 1 (junctiontoambientair) 1. 160-pin, qfp only. ?46 c/w p dd power dissipation ? 0.26 w
dc characteristics 6-3 table 6.3 scsi signals (open drain)?sd[7:0], sdp/, req/, msg/, i_o/, c_d/, atn/, ack/, bsy/, sel/, rst/ symbol parameter min max units conditions v ih input high voltage 2.0 v dd +0.5 v ? v il input low voltage v ss = ? 0.5 0.8 v ? v hys hysteresis 300 ? mv ? v ol output low voltage v ss 0.5 v i ol =48ma i in input leakage current ? 10 10 a? i nr input leakage (scsi rst) ? 200 50 a? i oz 3-state leakage current ? 10 10 a? table 6.4 input signals?bg/, boff/, reset/, cs/, bs, big-lit/, bclk, sclk symbol parameter min max units conditions v ih input high voltage 2.0 v dd +0.5 v ? v il input low voltage v ss ? 0.5 0.8 v ? i in input leakage current ? 1.0 1.0 a? table 6.5 output signals (totem pole)?sdir[7:0], sdirp, bsydir, seldir, rstdir, tgs, igs symbol parameter min max units conditions v oh output high voltage 2.4 v dd vi oh = ? 4ma v ol output low voltage v ss 0.4 v i ol =4ma i oh output high current ? 2.0 ? ma v oh =v dd ? 0.5 v i ol output low current 4.0 ? ma v ol =0.4v
6-4 electrical specifications table 6.6 output signals (totem pole)?fetch/, irq/ symbol parameter min max units conditions v oh output high voltage 2.4 v dd vi oh = ? 8ma v ol output low voltage v ss 0.4 v i ol =8ma i oh output high current ? 4.0 ? ma v oh =v dd ? 0.5 v i ol output low current 8.0 ? ma v ol =0.4v table 6.7 output signals (totem pole)?slack/, master symbol parameter min max units conditions v oh output high voltage 2.4 v dd vi oh = ? 16 ma v ol output low voltage v ss 0.4 v i ol =16ma i oh output high current ? 8.0 ? ma v oh =v dd ? 0.5 v i ol output low current 16.0 ? ma v ol =0.4v table 6.8 3-state output signals?a[31:6], fc[2:0], sc[1:0], upso-tt0/, cbreq/-tt1/, br/ symbol parameter min max units conditions v oh output high voltage 2.4 v dd vi oh = ? 16 ma v ol output low voltage v ss 0.4 v i ol =16ma i oh output high current ? 8.0 ? ma v oh =v dd ? 0.5 v i ol output low current 16.0 ? ma v ol =0.4v i oz 3-state leakage current ? 10 10 a?
dc characteristics 6-5 table 6.9 bidirectional signals (totem pole outputs)?a[5:0], d[31:0], dp[3:0], ds/-dle, as/-ts/, rw/, siz[1:0], berr/-tea/, halt/-tip/, bgack-bb/, cback/-tbi/, sterm/-ta/ symbol parameter min max units conditions v ih input high voltage 2.0 v dd +0.5 v ? v il input low voltage v ss ? 0.5 0.8 v ? v oh output high voltage 2.4 v dd vi oh = ? 16 ma v ol output low voltage v ss 0.4 v i ol =16ma i oh output high current ? 8.0 ? ma v oh =v dd ? 0.5 v i ol output low current 16.0 ? ma v ol =0.4v i in input leakage current ? 10 10 a? i oz 3-state leakage current ? 10 10 a? table 6.10 capacitance symbol parameter min max units conditions c i input capacitance of input pads ? 7 pf ? c io input capacitance of i/o pads ? 10 pf ?
6-6 electrical specifications 6.2 symbios tolerant specifications table 6.11 tolerant active negation technology electrical characteristics 1 1. these values are guaranteed by period characterization. symbol parameter min typ max units test conditions v oh 2 2. active negation outputs only: data, parity, req, ack. output high voltage 2.5 3.1 3.5 v i oh =2.5ma v ol output low voltage 0.1 0.2 0.5 v i ol =48ma v ih input high voltage 2.0 ? 7.0 v ? v il input low voltage ? 0.5 ? 0.8 v referenced to v ss v ik input clamp voltage ? 0.66 ? 0.74 ? 0.77 v v dd =min;i i = ? 20 ma v th threshold, high to low 1.1 1.2 1.3 v ? v tl threshold, low to high 1.5 1.6 1.7 v ? v th -v tl hysteresis 300 350 400 mv ? i oh 2 output high current 2.5 15 24 ma v oh =2.5v i ol output low current 100 150 200 ma v ol =0.5v i osh 2 short-circuit output high current ? ? 625 ma output driving low, pin shorted to v dd supply 3 3. single pin only. irreversible damage may occur if sustained for one second. i osl short-circuit output low current ? ? 95 ma output driving high, pin shorted to v ss supply i lh input high leakage ? 0.05 10 a ? 0.5 < v dd <5.25v pin =2.7v i ll input low leakage ? ? 0.05 ? 10 a ? 0.5 < v dd <5.25v pin =0.5v r i input resistance ? 20 ? m ? scsi pins 4 4. scsi reset pin has 10 k ? pull-up resistor. c p capacitance per pin 6 8 10 pf qfpp t r 2 rise time, 10% to 90% 9.7 15.0 18.5 ns figure 6.1 t f fall time, 90% to 10% 5.2 8.1 14.7 ns figure 6.1 dv h /dt slew rate, low to high 0.15 0.23 0.49 v/ns figure 6.1 dv l /dt slew rate, high to low 0.19 0.37 0.67 v/ns figure 6.1 electrostatic discharge 2 ? ? kv mil-std-883c; 3015.7 latch-up 100 ? ? ma ? filterdelay 202530ns figure 6.2 extended filter delay 40 50 60 ns figure 6.2
symbios tolerant specifications 6-7 figure 6.1 rise and fall time test conditions figure 6.2 scsi input filtering + ? 2.5 v 47 ? 20 pf req/ or ack/ input t 1 v th note: t 1 is the input filtering period, register programmable to either 30 or 60 ns.
6-8 electrical specifications figure 6.3 hysteresis of scsi receiver 1 0 received logic level input voltage (volts) 1.1 1.3 1.5 1.7
symbios tolerant specifications 6-9 figure 6.4 input current as a function of input voltage figure 6.5 output current as a function of output voltage +40 +20 0 ? 20 ? 40 ? 4 0 4 8 12 16 ? = 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) 0 ? 200 ? 400 ? 600 ? 800 012345 output voltage (volts) output source current (milliamperes) output voltage (volts) 0123 45 100 80 60 40 20 0
6-10 electrical specifications 6.3 ac specifications the ac characteristics described in this section apply over the operating voltage and temperature range, 4.75 > vdd > 5.25 v and 0 c = > = ta = < = 70 = c. output timings are based on worst case conditions (4.75 v, 70 c) and worst case processing using the following termination. the simulation load of the i/o pads is 120 pf, all timings in the specification are taken from the 10% and 90% points with respect to the specified vol and voh of the waveforms. figure 6.6 clock timing bclk, sclk t 1 t 3 t 4 t 2 table 6.12 SYM53C710 bus mode 1 clock timings symbol parameter min max units t 1 bus clock cycle time (t bclk )40 dc ns scsi clock cycle time (t sclk ) 1 15 60 ns t 2 bclk low time 2 17 ? ns sclk low time 2 7?ns t 3 bclk high time 2 17 ? ns sclk high time 2 7?ns t 4 bclk slew rate 1 ? v/ns sclk slew rate 1 ? v/ns 1. this parameter must be met to ensure scsi timings are within specification. 2. duty cycle not to exceed 60/40.
ac specifications 6-11 table 6.13 SYM53C710 bus mode 2 clock timings symbol parameter min max units t 1 bus clock cycle time (t bclk )30 dc ns scsi clock cycle time (t sclk ) 1 1. this parameter must be met to ensure scsi timings are within specification. 15 60 ns t 2 bclk low time 2 2. duty cycle not to exceed 60/40. 14 ? ns sclk low time 2 7?ns t 3 bclk high time 2 14 ? ns sclk high time 2 7?ns t 4 bclk slew rate 1 ? v/ns sclk slew rate 1 ? v/ns table 6.14 SYM53C710-1 bus mode 1 clock timings symbol parameter min max units t 1 bus clock cycle time (t bclk )30 dc ns scsi clock cycle time (t sclk ) 1 1. this parameter must be met to ensure scsi timings are within specification. 15 60 ns t 2 bclk low time 2 2. duty cycle not to exceed 60/40. 13 ? ns sclk low time 2 7?ns t 3 bclk high time 2 13 ? ns sclk high time 2 7?ns t 4 bclk slew rate 1 ? v/ns sclk slew rate 1 ? v/ns
6-12 electrical specifications figure 6.7 chip reset timing waveforms table 6.15 SYM53C710-1 bus mode 2 clock timings symbol parameter min max units t 1 bus clock cycle time (t bclk )25 dc ns scsi clock cycle time (t sclk ) 1 1. this parameter must be met to ensure scsi timings are within specification. 15 60 ns t 2 bclk low time 2 2. duty cycle not to exceed 60/40. 11 ? ns sclk low time 2 7?ns t 3 bclk high time 2 11 ? ns sclk high time 2 7?ns t 4 bclk slew rate 1 ? v/ns sclk slew rate 1 ? v/ns bclk reset/ t 1 t 2 table 6.16 chip reset timings 1 1. this timing is only required to ensure clock-for-clock repeatability after reset/ is deasserted. symbol parameter min max units t 1 reset pulse width 10 ? bclk t 2 reset deasserted setup to bclk high 10 ? ns
ac specifications 6-13 figure 6.8 irq timing waveforms bclk irq/ t 3 t 2 t 1 table 6.17 irq timings symbol parameter min max units t 1 bclk high to irq/ asserted ? 20 ns t 2 bclk high to irq/ deasserted ? 58 ns t 3 irq/ assertion time 3 ? bclk
6-14 electrical specifications 6.4 bus mode 1 slave cycle 6.4.1 bus mode 1 slave read sequence 1. the read/write, address, and size lines are asserted by the cpu. 2. address strobe is asserted by the cpu. 3. chip select is validated by the SYM53C710 on any following rising edge of bclk. 4. cache burst acknowledge is deasserted by the SYM53C710. 5. two clock cycles of wait state are inserted and the data lines are asserted by the SYM53C710. 6. slave acknowledge is asserted by the SYM53C710 if the cycle ends normally, or bus error is asserted if a bus error is detected. 7. synchronous cycle termination is asserted by memory. 8. address strobe is deasserted by the cpu. 9. slave acknowledge or bus error is deasserted by the SYM53C710, and the data lines are 3-stated by the SYM53C710.
bus mode 1 slave cycle 6-15 table 6.18 SYM53C710 bus mode 1 slave read timings symbol parameter min max units t 1 as/setuptocs/clockedactive 5 ? ns t 2 a[5:0], siz[1:0], r_w/ setup to as/ 4 ? ns t 3 a[5:0], siz[1:0], r_w/ hold from as/ 8 ? ns t 4 cs/ setup to bclk high after as/ 5 ? ns t 5 cs/ hold from bclk high after as/ 5 ? ns t 6 bclk high to cback/ high 5 26 ns t 7 as/ high to cback/ low 3 17 ns t 8 bclk high to slack/, berr/ low ? 22 ns t 9 as/ high to slack/, berr/ high ? 22 ns t 10 sterm/ (input) setup to bclk high 3 ? ns t 11 sterm/ (input) hold from bclk high 7 ? ns t 12 bclk high to data bus driven 8 28 ns t 13 bclk high to read data valid ? 75 ns t 14 as/ high to data bus high-z 7 28 ns
6-16 electrical specifications table 6.19 SYM53C710-1 bus mode 1 slave read timings 1 1. the SYM53C710 must see address strobes paired up with synchronous cycle terminations, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 as/setuptocs/clockedactive 5 ? ns t 2 a[5:0], siz[1:0], r_w/ setup to as/ 4 ? ns t 3 a[5:0], siz[1:0], r_w/ hold from as/ 8 ? ns t 4 cs/ setup to bclk high after as/ 5 ? ns t 5 cs/ hold from bclk high after as/ 5 ? ns t 6 bclk high to cback/ high 5 20 ns t 7 as/ high to cback/ low 3 15 ns t 8 bclk high to slack/, berr/ low ? 20 ns t 9 as/ high to slack/, berr/ high ? 20 ns t 10 sterm/ (input) setup to bclk high 2 ? ns t 11 sterm/ (input) hold from bclk high 7 ? ns t 12 bclk high to data bus driven 8 28 ns t 13 bclk high to read data valid ? 60 ns t 14 as/ high to data bus high-z 7 28 ns
bus mode 1 slave cycle 6-17 figure 6.9 bus mode 1 slave read cycle 1 as/ (driven by cpu) a[5:0], siz[1:0] r_w/ cs/ (driven by cpu) cback/ (driven by SYM53C710) slack/ sterm/ (driven by cpu) 2 read data/ (driven by SYM53C710) (driven by cpu) bclk t 8 t 9 t 7 t 6 t 1 t 13 t 14 t 12 t 11 t 10 valid t 2 t 3 t 4 start select wait wait ack berr/ (driven by SYM53C710) t 5 valid read data 1. shaded area indicates that the signal is a don?t care. 2. this signal may be driven by the SYM53C710 if the enable ack (ea) bit is set (dcntl, bit 5). see explanation in chapter 2 for use of this signal as an output.
6-18 electrical specifications 6.4.2 bus mode 1 slave write sequence 1. the read/write, address, and size lines are asserted by the cpu. 2. address strobe is asserted by the cpu. 3. chip select is validated by the SYM53C710 on any following rising edge of bclk. 4. cache burst acknowledge is deasserted by the SYM53C710. 5. the data lines are asserted by the cpu. 6. slave acknowledge is asserted by the SYM53C710 if the cycle ends normally, or bus error is asserted if a bus error is detected. 7. sterm/ is sampled. 8. address strobe is deasserted by the cpu. 9. slave acknowledge or bus error is deasserted by the SYM53C710. table 6.20 SYM53C710 bus mode 1 slave write timings symbol parameter min max units t 1 as/setuptocs/clockedactive 5 ? ns t 2 a[5:0], siz[1:0], r_w/ setup to as/ 4 ? ns t 3 a[5:0], siz[1:0], r_w/ hold from as/ 8 ? ns t 4 cs/ setup to bclk high after as/ 5 ? ns t 5 cs/ hold from bclk high after as/ 5 ? ns t 6 bclk high to cback/ high 5 26 ns t 7 as/ high to cback/ low 3 17 ns t 8 bclk high to slack/, berr/ low ? 22 ns t 9 as/ high to slack/, berr/ high ? 22 ns t 10 sterm/ (input) setup to bclk high 3 ? ns t 11 sterm/ (input) hold from bclk high 7 ? ns t 12 write data setup to bclk low 4 ? ns t 13 write data hold from bclk low 6 ? ns
bus mode 1 slave cycle 6-19 table 6.21 SYM53C710-1 bus mode 1 slave write timings 1 1. the SYM53C710 must see address strobes paired up with synchronous cycle terminations, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 as/setuptocs/clockedactive 5 ? ns t 2 a[5:0], siz[1:0], r_w/ setup to as/ 4 ? ns t 3 a[5:0], siz[1:0], r_w/ hold from as/ 8 ? ns t 4 cs/ setup to bclk high after as/ 5 ? ns t 5 cs/ hold from bclk high after as/ 5 ? ns t 6 bclk high to cback/ high 5 20 ns t 7 as/ high to cback/ low 3 15 ns t 8 bclk high to slack/, berr/ low ? 20 ns t 9 as/ high to slack/, berr/ high ? 20 ns t 10 sterm/ (input) setup to bclk high 2 ? ns t 11 sterm/ (input) hold from bclk high 7 ? ns t 12 write data setup to bclk low 4 ? ns t 13 write data hold from bclk low 6 ? ns
6-20 electrical specifications figure 6.10 bus mode 1 slave write cycle 1 as/ (driven by cpu) a[5:0], siz[1:0] r_w/ cs/ (driven by cpu) cback/ (driven by SYM53C710) slack/ berr/ sterm/ (driven by cpu) 2 write data/ (driven by cpu) (driven by cpu) bclk t 12 t 13 t 11 t 8 t 9 t 7 t 6 t 5 t 2 t 3 (driven by SYM53C710) t 4 t 1 t 10 start select wait wait ack valid valid write data 1. shaded area indicates that the signal is a don?t care. 2. this signal may be driven by the SYM53C710 if the enable ack (ea) bit is set (dcntl, bit 5). see explanation in chapter 2 for use of this signal as an output.
host bus arbitration 6-21 6.5 host bus arbitration 6.5.1 bus arbitration sequence 1. the SYM53C710 internally determines bus mastership is required. if appropriate, fetch/ is asserted. 2. bus request is asserted. 3. the SYM53C710 waits for bus grant and checks that bus grant acknowledge is deasserted. then the SYM53C710 asserts bus grant acknowledge and master, and deasserts bus request on the next rising edge of bclk.
6-22 electrical specifications table 6.22 SYM53C710 bus mode 1 host bus arbitration timings 1 1. the SYM53C710 periodically asserts the br/ signal and receives a scsi interrupt at the same time. when this happens, the chip waits for the bg/ signal to complete the normal bus arbitration handshake. the chip no longer wants host bus access. it deasserts the br/, master/, and all control lines after one bclk and does not assert ts/, the signal that indicates a valid bus cycle is starting. the chip generates an interrupt, which the system may then service. symbol parameter min max unit t 1 sc0hightobr/low 2 2. when the snoop mode bit (ctest8, bit 0) is set to 1. 12bclk t 2 bclk high to sc0 low on start phase of last cycle 2 528ns t 3 bclk high to br/ low 4 20 ns t 4 bclk high to br/ high 5 25 ns t 5 bg/ setup to bclk high (any rising edge after br/) 4?ns t 6 bg/ hold from bclk high (any rising edge after br/) 5?ns t 7 bgack/ setup to bclk high (any rising edge after br/) 5?ns t 8 bclk high to bgack/ low 4 24 ns t 9 bclk high to bgack/ high 3 15 ns t 10 bclk high to bgack/ high-z 7 32 ns t 11 bclk high to master/ low 5 22 ns t 12 bclk high to master/ high 6 26 ns t 13 bclk high to fetch/ low 5 36 ns t 14 bclk high to fetch/ high 5 36 ns t 15 fetch/ low to br/ low 1 2 bclk t 16 bgack/ high to fetch/ high 3 3. during a retry operation, fetch/ remains low until a successful completion of the opcode fetch or a fatal bus error. 12bclk
host bus arbitration 6-23 table 6.23 SYM53C710-1 bus mode 1 host bus arbitration timings 1 1. the SYM53C710 periodically asserts the br/ signal and receives a scsi interrupt at the same time. when this happens, the chip waits for the bg/ signal to complete the normal bus arbitration handshake. the chip no longer wants host bus access. it deasserts the br/, master/, and all control lines after one bclk and does not assert ts/, the signal that indicates a valid bus cycle is starting. the chip generates an interrupt, which the system may then service. symbol parameter min max unit t 1 sc0hightobr/low 2 2. when the snoop mode bit (ctest8, bit 0) is set to 1. 12bclk t 2 bclk high to sc0 low on start phase of last cycle 2 522ns t 3 bclk high to br/ low 4 16 ns t 4 bclk high to br/ high 5 21 ns t 5 bg/ setup to bclk high (any rising edge after br/) 4?ns t 6 bg/ hold from bclk high (any rising edge after br/) 5?ns t 7 bgack/ setup to bclk high (any rising edge after br/) 5?ns t 8 bclk high to bgack/ low 4 20 ns t 9 bclk high to bgack/ high 3 12 ns t 10 bclk high to bgack/ high-z 7 28 ns t 11 bclk high to master/ low 5 18 ns t 12 bclk high to master/ high 6 21 ns t 13 bclk high to fetch/ low 5 28 ns t 14 bclk high to fetch/ high 5 28 ns t 15 fetch/ low to br/ low 1 2 bclk t 16 bgack/ high to fetch/ high 3 3. during a retry operation, fetch/ remains low until a successful completion of the opcode fetch or a fatal bus error. 12bclk
6-24 electrical specifications figure 6.11 bus mode 1 host bus arbitration cycle 1 sc0 (internal bus request) br/ bg/ (driven by cpu) 2 as/, sterm/ (driven by cpu) bgack/ 3 master/ (driven by SYM53C710) fetch (driven by SYM53C710) (driven by cpu to start of (driven by SYM53C710) (driven by SYM53C710) grant cycle, driven by SYM53C710 from start of grant cycle.) bclk t 13 t 15 t 16 t 12 t 11 t 9 t 8 t 7 t 5 t 6 t 1 t 3 t 14 t 10 t 4 t 2 last owner request grant own start ack start ack release (first cycle) (last cycle) 1. shaded area indicates that the signal is a don?t care. the SYM53C710 inserts a fairness delay of 5?8 clocks between host bus arbitrations. 2. in order for bus grant to be recognized, as/ and sterm/ must be false. 3. if the fast arbitration bit is set (dcntl, bit 1) the SYM53C710 drives the bus grant acknowledge signal as soon as it receives a bus grant. one clock cycle of arbitration is saved.
bus mode 1 fast arbitration 6-25 6.6 bus mode 1 fast arbitration 6.6.1 fast arbitration sequence 1. the SYM53C710 internally determines bus mastership is required. if appropriate, fetch/ is asserted. 2. bus request is asserted. 3. the SYM53C710 waits for bus grant. then the SYM53C710 becomes bus master asynchronously on the leading edge of bg/. the SYM53C710 asynchronously asserts bus grant acknowledge and master, and deasserts bus request. 4. the SYM53C710 issues a start cycle on the next rising edge of bclk. note: in fast arbitration mode, the SYM53C710 takes bus ownership on the assertion of bg/ regardless of the state of br/ or bgack/.
6-26 electrical specifications table 6.24 SYM53C710 bus mode 1 fast arbitration timings symbol parameter min max units t 1 bclk high to br/ asserted ? 20 ns t 2 bg/ setup to bclk high 16 ? ns t 3 bg/ asserted to br/ deasserted ? 22 ns t 4 bg/ asserted to bgack/ asserted ? 20 ns t 5 bg/ asserted to master/ asserted ? 16 ns t 6 bg/ hold after br/ deasserted 1 1. bg/ may not be asserted prior to br/. 0?ns t 7 br/ asserted to bg/ asserted 0 ? ns t 8 bg/tobclkhighinackphaseof last cycle ?29ns table 6.25 SYM53C710-1 bus mode 1 fast arbitration timings symbol parameter min max units t 1 bclk high to br/ asserted ? 16 ns t 2 bg/ setup to bclk high 16 ? ns t 3 bg/ asserted to br/ deasserted ? 18 ns t 4 bg/ asserted to bgack/ asserted ? 16 ns t 5 bg/ asserted to master/ asserted ? 14 ns t 6 bg/ hold after br/ deasserted 1 1. bg/ may not be asserted prior to br/. 0?ns t 7 br/ asserted to bg/ asserted 0 ? ns t 8 bg/tobclkhighinackphaseof last cycle ?29ns
bus mode 1 fast arbitration 6-27 figure 6.12 bus mode 1 fast arbitration 1 br/ bg/ (driven by cpu) 2 as/, sterm/ (driven by SYM53C710) bgack/ 3 master/ (driven by SYM53C710) fetch (driven by SYM53C710) (driven by cpu to start of (driven by SYM53C710) grant cycle, driven by SYM53C710 from start of grant cycle.) bclk t 4 t 5 t 8 t 2 t 7 t 6 t 3 t 1 request and grant start ack ack release (first cycle) (last cycle) 1. shaded area indicates that the signal is a don?t care. the SYM53C710 inserts a fairness delay of 5?8 clocks between host bus arbitrations. 2. in order for bus grant to be recognized, as/ and sterm/ must be false. 3. if the fast arbitration bit is set (dcntl, bit 1) the SYM53C710 drives the bus grant acknowledge signal as soon as it receives a bus grant. one clock cycle of arbitration is saved.
6-28 electrical specifications 6.7 bus mode 1 bus master cycle 6.7.1 bus mode 1 bus master read sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3. the SYM53C710 asserts the address and size lines. 4. the SYM53C710 asserts address strobe, cache burst request (if appropriate), and data strobe. 5. the SYM53C710 waits for synchronous termination, valid data, cache burst acknowledge, bus error, and halt. ? if cache burst acknowledge is asserted, attempt bursting. ? if bus error and halt are asserted, attempt a retry. ? if synchronous termination is asserted without bus error or halt, and the SYM53C710 requires more cycles, then return to step 3. 6. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge. 7. the SYM53C710 floats the control and address lines.
bus mode 1 bus master cycle 6-29 table 6.26 SYM53C710 bus mode 1 bus master read timings (noncache line and cache line burst) symbol parameter min max units t 1 boff/setuptobclkhigh 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to as/ driven 5 32 ns t 4 bclk low to as/ low 3 15 ns t 5 bclk low to as/ high 3 15 ns t 6 bclk high to as/ high-z 7 34 ns t 7 sterm/ (input) setup to bclk high 3 ? ns t 8 sterm/ (input) hold from bclk high 7 ? ns t 9 bclk high to a[31:0], siz[1:0] driven 5 28 ns t 10 bclk high to a[31:0], siz[1:0] valid 4 18 ns t 11 bclk high to a[31:0], siz[1:0] high-z 7 34 ns t 12 bclk high to r_w/, sc[1:0], fc[2:0], upso driven and valid 5 28 ns t 13 bclk high to r_w/, sc[1:0], fc[2:0], upso high-z 6 30 ns t 14 read data setup to bclk low 4 ? ns t 15 read data hold from bclk low 6 ? ns t 16 bclk high to ds/ driven 5 32 ns t 17 bclk low to ds/ low 3 16 ns t 18 bclk low to ds/ high 3 16 ns t 19 bclk high to ds/ high-z 7 34 ns t 20 bclk high to cbreq/ driven 5 30 ns t 21 bclk low to cbreq/ low 3 16 ns t 22 bclk low to cbreq/ high 3 16 ns t 23 bclk high to cbreq/ high-z 7 32 ns t 24 cback/setuptobclklow 8 ? ns t 25 cback/ hold from bclk low 4 ? ns t 26 berr/, halt/ setup to bclk low 6 ? ns t 27 berr/, halt/ hold from bclk low 4 ? ns
6-30 electrical specifications table 6.27 SYM53C710-1 bus mode 1 bus master read timings (noncache line and cache line burst) symbol parameter min max units t 1 boff/setuptobclkhigh 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to as/ driven 5 26 ns t 4 bclk low to as/ low 3 14 ns t 5 bclk low to as/ high 3 14 ns t 6 bclk high to as/ high-z 7 28 ns t 7 sterm/ (input) setup to bclk high 3 ? ns t 8 sterm/ (input) hold from bclk high 7 ? ns t 9 bclk high to a[31:0], siz[1:0] driven 5 24 ns t 10 bclk high to a[31:0], siz[1:0] valid 4 15 ns t 11 bclk high to a[31:0], siz[1:0] high-z 7 28 ns t 12 bclk high to r_w/, sc[1:0], fc[2:0], upso driven and valid 5 24 ns t 13 bclk high to r_w/, sc[1:0], fc[2:0], upso high-z 6 25 ns t 14 read data setup to bclk low 4 ? ns t 15 read data hold from bclk low 6 ? ns t 16 bclk high to ds/ driven 5 25 ns t 17 bclk low to ds/ low 3 14 ns t 18 bclk low to ds/ high 3 14 ns t 19 bclk high to ds/ high-z 7 28 ns t 20 bclk high to cbreq/ driven 5 25 ns t 21 bclk low to cbreq/ low 3 14 ns t 22 bclk low to cbreq/ high 3 14 ns t 23 bclk high to cbreq/ high-z 7 26 ns t 24 cback/setuptobclklow 8 ? ns t 25 cback/ hold from bclk low 4 ? ns t 26 berr/, halt/ setup to bclk low 6 ? ns t 27 berr/, halt/ hold from bclk low 4 ? ns
bus mode 1 bus master cycle 6-31 figure 6.13 bus mode 1 bus master read cycle (noncache line burst) 1 siz[1:0], a[31:0] r_w/ sc[1:0] 2 , fc[2:0] read data (driven by memory) ds/ (driven by SYM53C710) cbreq/ (driven by SYM53C710) cback/ (driven by memory) berr/ halt/ t 27 t 26 t 23 t 22 #1 (driven by memory) t 25 data #2 t 21 t 20 t 19 t 15 t 16 t 17 #2 upso (driven by SYM53C710 ) t 24 t 18 t 14 (driven by SYM53C710) t 12 t 13 t 11 t 9 t 10 sterm/ (driven by memory) t 8 t 7 t 6 t 3 t 4 t 5 as/ (driven by SYM53C710) boff/ (driven by cpu) t 2 t 1 own start ack start wait ack release bclk valid for all transfers within this ownership addr #1 old addr #2 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
6-32 electrical specifications figure 6.14 bus mode 1 bus master read cycle (cache line burst) 1 siz[1:0], a[31:0] r_w/ sc[1:0] 2 , fc[2:0] read data (driven by memory) ds/ (driven by SYM53C710) cbreq/ (driven by SYM53C710) cback/ (driven by memory) berr/ halt/ t 27 t 26 t 23 t 22 #1 (driven by memory ) t 25 t 21 t 20 t 19 t 15 t 16 t 17 #4 upso (driven by SYM53C710 ) t 18 t 14 (driven by SYM53C710) old t 12 t 13 t 11 t 9 t 10 sterm/ (driven by memory) t 8 t 7 t 6 t 3 t 4 t 5 as/ (driven by SYM53C710) boff/ (driven by cpu) t 2 t 1 own start ack ack ack ack release bclk t 24 #2 #3 valid for all transfers within this ownership addr #1, size = 3 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
bus mode 1 bus master cycle 6-33 6.7.2 bus mode 1 bus master write sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3. the SYM53C710 asserts the address, size, and data lines. 4. the SYM53C710 asserts address strobe and cache burst request (and data strobe if read). 5. the SYM53C710 asserts data strobe. 6. the SYM53C710 waits for synchronous termination, cache burst acknowledge, bus error, and halt. ? if cache burst acknowledge is asserted, attempt bursting. ? if bus error and halt are asserted, attempt a retry. ? if synchronous termination is asserted without bus error or halt, and the SYM53C710 requires more cycles, then return to step 3. 7. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge 8. the SYM53C710 floats the control, address, and data lines.
6-34 electrical specifications table6.28 SYM53C710busmode1masterwritetimings (noncache line and cache line burst) symbol parameter min max units t 1 boff/ setup to bclk high 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to as/ driven 5 32 ns t 4 bclk low to as/ low 3 15 ns t 5 bclk low to as/ high 3 15 ns t 6 bclk high to as/ high-z 7 34 ns t 7 sterm/ setup to bclk high 3 ? ns t 8 sterm/ hold from bclk high 7 ? ns t 9 bclk high to a[31:0], siz[1:0] driven 5 28 ns t 10 bclk high to a[31:0], siz[1:0] valid 4 18 ns t 11 bclk high to a[31:0], siz[1:0] high-z 7 34 ns t 12 bclk high to r_w/, sc[1:0], fc[2:0], upso driven and valid 5 28 ns t 13 bclk high to r_w/, sc[1:0], fc[2:0], upso high-z 6 30 ns t 14 bclk high to write data driven 6 34 ns t 15 bclk high to write data valid 6 24 ns t 16 bclk high to write data high-z 6 32 ns t 17 bclk high to ds/ driven 5 32 ns t 18 bclk low to ds/ low 3 16 ns t 19 bclk low to ds/ high 3 16 ns t 20 bclk high to ds/ high-z 7 34 ns t 21 bclk high to cbreq/ driven 5 30 ns t 22 bclk low to cbreq/ low 3 16 ns t 23 bclk low to cbreq/ high 3 16 ns t 24 bclk high to cbreq/ high-z 7 32 ns t 25 cback/setuptobclklow 8 ? ns t 26 cback/ hold from bclk low 4 ? ns t 27 berr/, halt/ setup to bclk low 6 ? ns t 28 berr/, halt/ hold from bclk low 4 ? ns
bus mode 1 bus master cycle 6-35 table 6.29 SYM53C710-1 bus mode 1 bus master write timings (noncache line and cache line burst) symbol parameter min max units t 1 boff/ setup to bclk high 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to as/ driven 5 26 ns t 4 bclk low to as/ low 3 14 ns t 5 bclk low to as/ high 3 14 ns t 6 bclk high to as/ high-z 7 28 ns t 7 sterm/ setup to bclk high 3 ? ns t 8 sterm/ hold from bclk high 7 ? ns t 9 bclk high to a[31:0], siz[1:0] driven 5 24 ns t 10 bclk high to a[31:0], siz[1:0] valid 4 15 ns t 11 bclk high to a[31:0], siz[1:0] high-z 7 28 ns t 12 bclk high to r_w/, sc[1:0], fc[2:0], upso driven and valid 5 24 ns t 13 bclk high to r_w/, sc[1:0], fc[2:0], upso high-z 6 25 ns t 14 bclk high to write data driven 6 28 ns t 15 bclk high to write data valid 6 20 ns t 16 bclk high to data high-z 6 26 ns t 17 bclk high to ds/ driven 5 25 ns t 18 bclk low to ds/ low 3 14 ns t 19 bclk low to ds/ high 3 14 ns t 20 bclk high to ds/ high-z 7 28 ns t 21 bclk high to cbreq/ driven 5 25 ns t 22 bclk low to cbreq/ low 3 14 ns t 23 bclk low to cbreq/ high 3 14 ns t 24 bclk high to cbreq/ high-z 7 26 ns t 25 cback/setuptobclklow 8 ? ns t 26 cback/ hold from bclk low 4 ? ns t 27 berr/, halt/ setup to bclk low 6 ? ns t 28 berr/, halt/ hold from bclk low 4 ? ns
6-36 electrical specifications figure 6.15 bus mode 1 bus master write cycle (noncache line burst) 1 a[31:0], siz[1:0] r_w/ sc[1:0] 2 , fc[2:0] write data (driven by SYM53C710) ds/ (driven by SYM53C710) cbreq/ (driven by SYM53C710) cback/ (driven by memory) berr/ halt/ t 28 t 27 t 24 old (driven by memory) t 26 t 22 t 21 t 20 t 17 upso (driven by SYM53C710 ) t 19 t 14 (driven by SYM53C710) old t 12 t 13 t 11 t 9 sterm/ (driven by memory) t 8 t 7 as/ (driven by SYM53C710) boff/ (driven by cpu) own start ack start wait ack release bclk t 25 t 23 t 18 t 15 t 16 data #1 valid for all transfers within this ownership addr #1 addr #2 data #2 old t 10 t 6 t 3 t 4 t 5 t 2 t 1 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
bus mode 1 bus master cycle 6-37 figure 6.16 bus mode 1 bus master write cycle (cache line burst) 1 a[31:0], siz[1:0] r_w/ sc[1:0] 2 , fc[2:0] write data (driven by SYM53C710) ds/ (driven by SYM53C710) cbreq/ (driven by SYM53C710) cback/ (driven by memory) berr/ halt/ (driven by memory) t 19 t 15 t 17 t 18 upso (driven by SYM53C710 ) t 20 (driven by SYM53C710) old t 14 t 13 t 11 t 9 sterm/ (driven by memory) t 8 t 7 as/ (driven by SYM53C710) boff/ (driven by cpu) own start ack ack ack ack release bclk old data #1 data #2 data #3 data #4 t 16 t 12 addr #1, size = 3 valid for all transfers within this ownership t 28 t 27 t 24 t 23 t 26 t 22 t 21 t 25 t 6 t 3 t 4 t 5 t 2 t 1 t 10 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
6-38 electrical specifications 6.8 bus mode 2 slave cycle 6.8.1 bus mode 2 slave read sequence 1. the read/write, address, transfer start, and the size lines are asserted by the cpu. 2. chip select is validated by the SYM53C710 on any following rising edge of bclk. 3. transfer burst inhibit is asserted. 4. transfer start is deasserted by the cpu. 5. three clock cycles of wait state are inserted and the data lines are asserted. 6. slave acknowledge is asserted by the SYM53C710, if no errors are detected. 7. if a bus error is detected, only transfer error acknowledge is asserted and the bus cycle ends on the next rising edge of bclk. 8. slave acknowledge or transfer error acknowledge is deasserted. 9. the SYM53C710 waits for transfer acknowledge to be asserted and then ends the slave cycle, if no errors are detected. 10. the data lines are 3-stated by the SYM53C710.
bus mode 2 slave cycle 6-39 table 6.30 SYM53C710 bus mode 2 slave read timings 1 1. the SYM53C710 must see transfer starts paired up with transfer acknowledges, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 ts/ setup to bclk high 4 ? ns t 2 ts/ hold from bclk high 4 ? ns t 3 cs/ setup to any bclk high after ts/ 5 ? ns t 4 cs/ hold from any bclk high after ts/ 5 ? ns t 5 bclk high to tbi/ low 5 30 ns t 6 bclk high to tbi/ high 4 22 ns t 7 bclk high to slack/, tea/ low 5 20 ns t 8 bclk high to slack/, tea/ high 4 20 ns t 9 ta/ setup to bclk high during or after slack/, tea/ 9 ? ns t 10 ta/ hold from bclk high during or after slack/, tea/ 5 ? ns t 11 bclk high to data bus driven 8 28 ns t 12 bclk high to read data valid ? 75 ns t 13 bclk high to data bus high-z 7 30 ns t 14 a[5:0], siz[1:0], r_w/ setup to bclk high 4 ? ns t 15 a[5:0], siz[1:0], r_w/ hold from bclk high 12 ? ns
6-40 electrical specifications table 6.31 SYM53C710-1 bus mode 2 slave read timings 1 1. the SYM53C710 must see transfer starts paired up with transfer acknowledges, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 ts/ setup to bclk high 4 ? ns t 2 ts/ hold from bclk high 4 ? ns t 3 cs/ setup to bclk high after ts/ 5 ? ns t 4 cs/ hold from bclk high after ts/ 5 ? ns t 5 bclk high to tbi/ low 5 25 ns t 6 bclk high to tbi/ high 4 18 ns t 7 bclk high to slack/, tea/ low 5 17 ns t 8 bclk high to slack/, tea/ high 4 17 ns t 9 ta/ setup to bclk high during or after slack/, tea/ 9 ? ns t 10 ta/ hold from bclk high during or after slack/, tea/ 5 ? ns t 11 bclk high to data bus driven 8 28 ns t 12 bclk high to read data valid ? 60 ns t 13 bclk high to data bus high-z 7 25 ns t 14 a[5:0], siz[1:0], r_w/ setup to bclk high 4 ? ns t 15 a[5:0], siz[1:0], r_w/ hold from bclk high 12 ? ns
bus mode 2 slave cycle 6-41 figure 6.17 bus mode 2 slave read cycle 1 ts/ (driven by cpu) cs/ (driven by cpu) tbi/ (driven by SYM53C710) slack/ tea/ ta / read data/ (driven by SYM53C710) a[5:0], siz[1:0] r_w/ bclk t 15 t 13 (driven by cpu) 2 t 2 start select wait wait wait (driven by SYM53C710) (driven by cpu) valid t 14 valid read data t 12 t 11 t 10 t 9 t 7 t 8 t 6 t 5 t 4 t 3 t 1 ack 1. shaded area indicates that the signal is a don?t care. 2. this signal may be driven by the SYM53C710 if the enable ack (ea) bit is set (dcntl, bit 5). see explanation in chapter 2 for the use of this signal as an output.
6-42 electrical specifications 6.8.2 bus mode 2 slave write sequence 1. the read/write, address, transfer start, and size lines are asserted by the cpu. 2. chip select is validated by the SYM53C710 on any following rising edge of bclk. 3. transfer burst inhibit is asserted. 4. transfer start is deasserted by the cpu. 5. the data lines are asserted by the cpu. 6. three clock cycles of wait state are inserted. 7. slave acknowledge is asserted by the SYM53C710, if no errors are detected. 8. if a bus error is detected, only transfer error acknowledge is asserted and the bus cycle ends on the next rising edge of bclk. 9. the SYM53C710 waits for transfer acknowledge to be asserted and then ends the slave cycle, if no errors are detected. 10. slave acknowledge or transfer error acknowledge is deasserted.
bus mode 2 slave cycle 6-43 table 6.32 SYM53C710 bus mode 2 slave write timings 1 1. the SYM53C710 must see transfer starts paired up with transfer acknowledges, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 ts/ setup to bclk high 4 ? ns t 2 ts/ hold from bclk high 4 ? ns t 3 cs/ setup to bclk high after ts/ 5 ? ns t 4 cs/ hold from bclk high after ts/ 5 ? ns t 5 bclk high to tbi/ low 5 30 ns t 6 bclk high to tbi/ high 4 22 ns t 7 bclk high to slack/, tea/ low 5 20 ns t 8 bclk high to slack/, tea/ high 4 20 ns t 9 ta/ setup to bclk high during or after slack/, tea/ 9 ? ns t 10 ta/ hold from bclk high during or after slack/, tea/ 5 ? ns t 11 valid write data setup to bclk high 5 ? ns t 12 validwritedataholdfrombclkhigh 14 ? ns t 13 a[5:0], siz[1:0], r_w/ setup to bclk high 4 ? ns t 14 a[5:0], siz(1:0], r_w/ hold from bclk high 12 ? ns
6-44 electrical specifications table 6.33 SYM53C710-1 bus mode 2 slave write timings 1 1. the SYM53C710 must see transfer starts paired up with transfer acknowledges, even though the slave cycle may not be intended for the SYM53C710. symbol parameter min max units t 1 ts/ setup to bclk high 4 ? ns t 2 ts/ hold from bclk high 4 ? ns t 3 cs/ setup to bclk high after ts/ 5 ? ns t 4 cs/ hold from bclk high after ts/ 5 ? ns t 5 bclk high to tbi/ low 5 25 ns t 6 bclk high to tbi/ high 4 18 ns t 7 bclk high to slack/, tea/ low 5 17 ns t 8 bclk high to slack/, tea/ high 4 17 ns t 9 ta/ setup to bclk high during or after slack/, tea/ 9 ? ns t 10 ta/ hold from bclk high during or after slack/, tea/ 5 ? ns t 11 valid write data setup to bclk high 5 ? ns t 12 validwritedataholdfrombclkhigh 14 ? ns t 13 a[5:0], siz[1:0], r_w/ setup to bclk high 4 ? ns t 14 a[5:0], siz(1:0], r_w/ hold from bclk high 12 ? ns
bus mode 2 slave cycle 6-45 figure 6.18 bus mode 2 slave write cycle 1 ts/ (driven by cpu) cs/ (driven by cpu) tbi/ (driven by SYM53C710) slack/ tea/ ta / write data/ (driven by cpu) a[5:0], siz[1:0] r_w/ bclk t 12 (driven by cpu) 2 t 2 start select wait wait wait (driven by SYM53C710) (driven by cpu) valid t 13 valid write data t 11 t 10 t 9 t 7 t 8 t 6 t 5 t 4 t 3 t 1 ack t 14 1. shaded area indicates that the signal is a don?t care. 2. this signal may be driven by the SYM53C710 if the enable ack (ea) bit is set (dcntl, bit 5). see explanation in chapter 2 for the use of this signal as an output.
6-46 electrical specifications 6.9 host bus arbitration 6.9.1 bus arbitration sequence 1. the SYM53C710 internally determines bus mastership is required. if appropriate, fetch/ is asserted. 2. bus request is asserted. 3. the SYM53C710 waits for bus grant and checks that bus busy is deasserted. then the SYM53C710 asserts bus busy and master, and deasserts bus request.
host bus arbitration 6-47 table 6.34 SYM53C710 bus mode 2 host bus arbitration timings 1 1. the SYM53C710 periodically asserts the br/ signal and receives a scsi interrupt at the same time. when this happens, the chip waits for the bg/ signal to complete the normal bus arbitration handshake. the chip no longer wants host bus access. it deasserts the br/, master/, and all control lines after one bclk, and does not assert ts/, the signal that indicates a valid bus cycle is starting. the chip next generates an interrupt, which the system may then service. symbol parameter min max units t 1 sc0hightobr/low 2 2. when the snoop mode bit (ctest8, bit 0) is set to 1. 12bclk t 2 bclk high to sc0 low on start phase of last cycle 2 528ns t 3 bclk high to br/ low 4 20 ns t 4 bclk high to br/ high 5 25 ns t 5 bg/ setup to bclk high (any rising edge after br/) 4 ? ns t 6 bg/holdfrombclkhigh(anyrisingedgeafterbr/) 5 ? ns t 7 bb/ setup to bclk high (any rising edge after br/) 4 ? ns t 8 bclk high to bb/ low 4 24 ns t 9 bclk high to bb/ high 3 19 ns t 10 bclk high to bb/ high-z 7 32 ns t 11 bclk high to master/ low 5 22 ns t 12 bclk high to master/ high 6 26 ? t 13 bclk high to fetch/ low 5 36 ns t 14 bclk high to fetch/ high 5 36 ns t 15 fetch/ low to br/ low 1 2 bclk t 16 bb/ high to fetch/ high 3 3. during a retry operation, fetch/ remains low until successful completion of an opcode fetch or a fatal bus error. 12bclk
6-48 electrical specifications table 6.35 SYM53C710-1 bus mode 2 host bus arbitration timings 1 1. the SYM53C710 will periodically assert the br/ signal and receives a scsi interrupt at the same time. when this happens, the chip will wait for the bg/ signal to complete the normal bus arbitration handshake. the chip no longer wants host bus access. it deasserts the br/, master/, and all control lines after one bclk, and does not assert ts/, the signal that indicates a valid bus cycle is starting. the chip will next generate an interrupt, which the system may then service. symbol parameter min max units t 1 sc0 high to br/ low 2 2. when the snoop mode bit (ctest8, bit 0) is set to 1. 12bclk t 2 bclk high to sc0 low on start phase of last cycle 2 522ns t 3 bclk high to br/ low 4 16 ns t 4 bclk high to br/ high 5 21 ns t 5 bg/ setup to bclk high (any rising edge after br/) 4 ? ns t 6 bg/ hold from bclk high (any rising edge after br/) 5 ? ns t 7 bb/setuptobclkhigh(anyrisingedgeafterbr/) 4 ? ns t 8 bclk high to bb/ low 4 20 ns t 9 bclk high to bb/ high 3 12 ns t 10 bclk high to bb/ high-z 7 28 ns t 11 bclk high to master/ low 5 18 ns t 12 bclk high to master/ high 6 21 ? t 13 bclk high to fetch/ low 5 28 ns t 14 bclk high to fetch/ high 5 28 ns t 15 fetch/ low to br/ low 1 2 bclk t 16 bb/ high to fetch/ high 3 3. during a retry operation, fetch/ will remain low until successful completion of an opcode fetch or a fatal bus error. 12bclk
host bus arbitration 6-49 figure 6.19 bus mode 2 host bus arbitration 1 sc0/ (internal bus request) br/ bg/ (driven by cpu) bb/ master/ (driven by SYM53C710) fetch (driven by SYM53C710) (driven by cpu to start of (driven by SYM53C710) (driven by cpu) grant cycle, driven by SYM53C710 from start of grant cycle.) 2 bclk t 13 t 15 t 16 t 12 t 11 t 9 t 8 t 7 t 5 t 6 t 1 t 3 t 14 t 10 t 4 t 2 last request grant start ack start ack release (first cycle) (last cycle) and own owner 1. shaded area indicates that the signal is a don?t care. the SYM53C710 will insert a fairness delay of 5?8 clocks between host bus arbitrations. 2. if the fast arbitration bit is set (dcntl, bit 1), the SYM53C710 will drive the bus grant acknowledge signal as soon as it receives a bus grant. one clock cycle of arbitration will be saved.
6-50 electrical specifications 6.10 bus mode 2 fast arbitration 6.10.1 fast arbitration sequence 1. the SYM53C710 determines bus mastership is required. if appropriate, fetch/ is asserted. 2. bus request is asserted. 3. the SYM53C710 waits for bus grant. the SYM53C710 becomes bus master asynchronously on the leading edge of bg/. then the SYM53C710 asynchronously asserts bus busy and master, and deasserts bus request. 4. the SYM53C710 issues a start cycle on the next rising edge of bclk. note: in fast arbitration mode, the SYM53C710 will take bus ownership on the assertion of bg/ regardless of the state of br/ or bb/.
bus mode 2 fast arbitration 6-51 table 6.36 SYM53C710 bus mode 2 fast arbitration timings symbol parameter min max units t 1 bclk high to br/ asserted ? 20 ns t 2 bg/ setup to bclk high 16 ? ns t 3 bg/ asserted to br/ deasserted ? 22 ns t 4 bg/ asserted to bb/ asserted ? 20 ns t 5 bg/ asserted to master/ asserted ? 16 ns t 6 bg/ hold after br/ deasserted 0 ? ns t 7 br/ asserted to bg/ asserted 0 ? ns t 8 bg/tobclkhigh,inackphaseoflastcycle ? 29 ns table 6.37 SYM53C710-1 bus mode 2 fast arbitration timings symbol parameter min max units t 1 bclk high to br/ asserted ? 16 ns t 2 bg/ setup to bclk high 16 ? ns t 3 bg/ asserted to br/ deasserted ? 18 ns t 4 bg/ asserted to bb/ asserted ? 16 ns t 5 bg/ asserted to master/ asserted ? 14 ns t 6 bg/ hold after br/ deasserted 1 1. bg/ may not be asserted prior to br/. 0?ns t 7 br/ asserted to bg/ asserted 0 ? ns t 9 bg/ to bclk high, in ack phase of last cycle ? 29 ns
6-52 electrical specifications figure 6.20 bus mode 2 fast arbitration 1 br/ bg/ (driven by cpu) 2 ta / (driven by SYM53C710) bb/ master/ (driven by SYM53C710) fetch (driven by SYM53C710) (driven by cpu to start of (driven by SYM53C710) grant cycle, driven by SYM53C710 from start of grant cycle.) bclk t 4 t 5 t 8 t 2 t 7 t 6 t 3 t 1 request and grant start ack ack release (first cycle) (last cycle) 1. shaded area indicates that the signal is a don?t care.
bus mode 2 bus master cycle 6-53 6.11 bus mode 2 bus master cycle 6.11.1 bus mode 2 bus master read sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3a. the SYM53C710 asserts transfer in progress and transfer start. 3b. the SYM53C710 asserts transfer start, address, and size lines. 4. the SYM53C710 deasserts transfer start. 5. the SYM53C710 waits for transfer acknowledge, valid data, transfer burst inhibit, and transfer error acknowledge. ? if transfer burst inhibit is not asserted, attempt cache bursting. ? if transfer error acknowledge and transfer acknowledge are asserted, attempt a retry. ? if transfer error acknowledge is asserted and transfer acknowledge is not asserted, a bus fault condition will be generated on the next rising edge of bclk. ? if transfer acknowledge is asserted and transfer error acknowledge is not asserted and the SYM53C710 requires more cycles,thenreturntostep3b. 6. the SYM53C710 deasserts the control and address lines. 7. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge.
6-54 electrical specifications table6.38 SYM53C710busmode2busmastercyclereadtimings (noncache line and cache line burst) symbol parameter min max units t 1 boff/ setup to bclk high 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to tip/ driven 5 32 ns t 4 bclk high to tip/ low 3 17 ns t 5 bclk high to tip/ high 3 16 ns t 6 bclk high to tip/ high-z 7 32 ns t 7 bclk high to ts/ driven 5 30 ns t 8 bclk high to ts/ low 3 14 ns t 9 bclk high to ts/ high 4 13 ns t 10 bclk high to ts/ high-z 7 32 ns t 11 ta/ setup to bclk high 9 ? ns t 12 ta/ hold from bclk high 5 ? ns t 13 bclk high to a[31:0], siz[1:0] driven 5 28 ns t 14 bclk high to a[31:0], siz[1:0] valid 5 18 ns t 15 bclk high to a[31:0], siz[1:0] high-z 7 32 ns t 16 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] driven and valid 5 30 ns t 17 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] high-z ? 32 ns t 18 read data setup to bclk high 5 ? ns t 19 read data hold from bclk high 6 ? ns t 20 read data setup to dle low 4 ? ns t 21 read data hold from dle low 6 ? ns t 22 tbi/ setup to bclk high 6 ? ns t 23 tbi/ hold from bclk high 4 ? ns t 24 tea/ setup to bclk high 9 ? ns t 25 tea/ hold from bclk high 5 ? ns
bus mode 2 bus master cycle 6-55 table 6.39 SYM53C710-1 bus mode 2 bus master read cycle timings (noncache line and cache line burst) symbol parameter min max units t 1 boff/ setup to bclk high 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to tip/ driven 5 26 ns t 4 bclk high to tip/ low 3 14 ns t 5 bclk high to tip/ high 3 14 ns t 6 bclk high to tip/ high-z 7 28 ns t 7 bclk high to ts/ driven 5 25 ns t 8 bclk high to ts/ low 3 12 ns t 9 bclk high to ts/ high 4 12 ns t 10 bclk high to ts/ high-z 7 28 ns t 11 ta/ setup to bclk high 9 ? ns t 12 ta/ hold from bclk high 5 ? ns t 13 bclk high to a[31:0], siz[1:0] driven 5 24 ns t 14 bclk high to a[31:0], siz[1:0] valid 5 15 ns t 15 bclk high to a[31:0], siz[1:0] high-z 7 28 ns t 16 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] driven and valid 5 25 ns t 17 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] high-z ? 28 ns t 18 read data setup to bclk high 5 ? ns t 19 read data hold from bclk high 6 ? ns t 20 read data setup to dle low 4 ? ns t 21 read data hold from dle low 6 ? ns t 22 tbi/ setup to bclk high 6 ? ns t 23 tbi/ hold from bclk high 4 ? ns t 24 tea/ setup to bclk high 9 ? ns t 25 tea/ hold from bclk high 5 ? ns
6-56 electrical specifications figure 6.21 bus mode 2 bus master read cycle (noncache line burst) 1 a[31:0], siz[1:0] r_w/ sc[1:0] 2 , fc[2:0] read data (driven by memory) dle (driven by memory) tbi/ (driven by memory) tea/ t 25 t 24 #1 t 23 t 19 tt[1:0] (driven by SYM53C710 ) t 22 t 18 (driven by SYM53C710) t 16 t 17 t 15 t 13 t 14 ta / (driven by memory) t 12 t 11 t 10 t 7 t 8 t 9 ts/ (driven by SYM53C710) boff/ (driven by cpu) t 2 t 1 own start ack start wait ack release bclk valid for all transfers within this ownership addr #1 addr #2 t 21 t 20 #2 t 4 t 6 t 5 t 3 tip/ (driven by SYM53C710) (driven by memory) 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero. old
bus mode 2 bus master cycle 6-57 figure 6.22 bus mode 2 bus master read cycle (cache line burst) 1 a[31:0], siz[1:0] r_w/ sc[1:0] 2 , fc[2:0] read data (driven by memory) dle (driven by memory) tbi/ (driven by memory) t 25 t 24 #4 tt[1:0] (driven by SYM53C710 ) (driven by SYM53C710) old t 17 t 15 t 13 t 14 ts/ (driven by SYM53C710) t 6 t 3 t 4 t 5 tip/ (driven by SYM53C710) boff/ (driven by cpu) t 2 t 1 own start ack ack ack ack release bclk #2 #3 valid for all transfers within this ownership addr #1, size = 3 t 23 t 22 t 21 t 20 t 19 #1 t 16 t 12 t 11 t 10 t 7 t 8 t 9 ta / (driven by memory) tea/ (driven by memory) 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
6-58 electrical specifications 6.11.2 bus mode 2 bus master write sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3a. the SYM53C710 asserts transfer in progress and transfer start. 3b. the SYM53C710 asserts transfer start, address, size lines, and data lines. 4. the SYM53C710 deasserts transfer start. 5. the sym53710 waits for transfer acknowledge, transfer burst inhibit, and transfer error acknowledge. ? if transfer burst inhibit is not asserted, attempt cache bursting. ? if transfer error acknowledge and transfer acknowledge are asserted, attempt a retry. ? if transfer error acknowledge is asserted and transfer acknowledge is not asserted, a bus fault condition will be generated. ? if transfer acknowledge is asserted, transfer error acknowledge is not asserted, and the SYM53C710 requires more cycles, return to step 3b. 6. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge. 7. the SYM53C710 floats the control, address, and data lines.
bus mode 2 bus master cycle 6-59 table6.40 SYM53C710busmode2busmasterwritetimings (noncache line and cache line burst) symbol parameter min max units t 1 boff/setuptobclkhigh 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to tip/ driven 5 32 ns t 4 bclk high to tip/ low 3 17 ns t 5 bclk high to tip/ high 3 16 ns t 6 bclk high to tip/ high-z 7 32 ns t 7 bclk high to ts/ driven 5 30 ns t 8 bclk high to ts/ low 3 14 ns t 9 bclk high to ts/ high 3 13 ns t 10 bclk high to ts/ high-z 7 32 ns t 11 ta/ setup to bclk high 9 ? ns t 12 ta / h o l d f r o m b c l k h i g h 5 ? n s t 13 bclk high to a[31:0], siz[1:0] driven 5 28 ns t 14 bclk high to a[31:0], siz[1:0] valid 3 18 ns t 15 bclk high to a[31:0], siz[1:0] high-z 7 32 ns t 16 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] driven and valid 5 30 ns t 17 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] high-z 5 32 ns t 18 bclk high to write data driven 5 34 ns t 19 bclk high to write data valid 7 24 ns t 20 bclk high to write data high-z 5 30 ns t 21 tbi/ setup to bclk high 6 ? ns t 22 tbi/ hold from bclk high 4 ? ns t 23 tea/ setup to bclk high 9 ? ns t 24 tea/ hold from bclk high 5 ? ns
6-60 electrical specifications table 6.41 SYM53C710-1 bus mode 2 bus master write timings (noncache line and cache line burst) symbol parameter min max units t 1 boff/ setup to bclk high 8 ? ns t 2 boff/ hold from bclk high 7 ? ns t 3 bclk high to tip/ driven 5 26 ns t 4 bclk high to tip/ low 3 14 ns t 5 bclk high to tip/ high 3 14 ns t 6 bclk high to tip/ high-z 7 28 ns t 7 bclk high to ts/ driven 5 25 ns t 8 bclk high to ts/ low 3 12 ns t 9 bclk high to ts/ high 3 12 ns t 10 bclk high to ts/ high-z 7 28 ns t 11 ta/ setup to bclk high 9 ? ns t 12 ta/ hold from bclk high 5 ? ns t 13 bclk high to a[31:0], siz[1:0] driven 5 24 ns t 14 bclk high to a[31:0], siz[1:0] valid 3 15 ns t 15 bclk high to a[31:0], siz[1:0] high-z 7 28 ns t 16 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] driven and valid 5 25 ns t 17 bclk high to r_w/, sc[1:0], fc[2:0], tt[1:0] high-z 5 28 ns t 18 bclk high to write data driven 5 28 ns t 19 bclk high to write data valid 7 18 ns t 20 bclk high to write data high-z 5 25 ns t 21 tbi/ setup to bclk high 6 ? ns t 22 tbi/ hold from bclk high 4 ? ns t 23 tea/ setup to bclk high 9 ? ns t 24 tea/ hold from bclk high 5 ? ns
bus mode 2 bus master cycle 6-61 figure 6.23 bus mode 2 bus master write cycle (noncache line burst) 1 ta / r_w/ sc[1:0] 2 , fc[2:0] write data (driven by SYM53C710) tbi/ (driven by memory) tea/ (driven by memory) old tt[1:0] (driven by SYM53C710 ) t 18 (driven by memory) old t 16 t 17 t 15 t 13 ts/ (driven by SYM53C710) t 11 tip/ (driven by SYM53C710) boff/ (driven by cpu) own start ack start wait ack release bclk t 19 t 20 data #1 valid for all transfers within this ownership addr #1 addr #2 data #2 old t 14 t 10 t 7 t 8 t 9 t 2 t 1 t 24 t 23 t 22 t 21 t 12 t 6 t 3 t 4 t 5 a[31:0], siz[1:0] (driven by SYM53C710) 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
6-62 electrical specifications figure 6.24 bus mode 2 bus master write cycle (cache line burst) 1 ta / r_w/ sc[1:0] 2 , fc[2:0] write data (driven by SYM53C710) tea/ (driven by memory) tt[1:0] (driven by SYM53C710 ) (driven by memory) t 16 t 17 ts/ (driven by SYM53C710) tip/ (driven by SYM53C710) boff/ (driven by cpu) own start ack ack ack ack release bclk valid for all transfers within this ownership t 6 t 3 t 4 t 5 a[31:0], siz[1:0] (driven by SYM53C710) t 24 t 23 t 22 t 21 t 18 old data #1 data #2 data #3 data #4 t 20 t 19 old t 15 t 13 t 14 addr #1, size = 3 t 12 t 11 t 10 t 7 t 8 t 9 t 2 t 1 tbi/ (driven by memory) 1. shaded area indicates that the signal is a don?t care. 2. sc[1:0] timings apply only if the snoop mode bit (ctest8, bit 0) equals zero.
bus mode 2 mux mode operation 6-63 6.12 bus mode 2 mux mode operation 6.12.1 mux mode read cycle (cache line and noncache line burst) mux mode read sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3a. the SYM53C710 asserts transfer in progress and transfer start. 3b. the SYM53C710 asserts the transfer start, address, and size lines. 4. the SYM53C710 deasserts transfer start and floats the address lines. 5. the SYM53C710 waits for transfer acknowledge, valid data driven on the data pins, transfer burst inhibit, and transfer error acknowledge. ? if transfer burst inhibit is not asserted, attempt cache bursting. ? if transfer error acknowledge and transfer acknowledge are asserted, attempt a retry. ? if transfer error acknowledge is asserted and transfer acknowledge is not asserted, a bus fault condition will be generated. ? if transfer acknowledge is asserted and transfer error acknowledge is not asserted and the SYM53C710 requires more cycles,thenreturntostep4. 6. the SYM53C710 deasserts the control lines. 7. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge. note: this mode of operation expects d[31:0] to be tied to a[31:0], respectively.
6-64 electrical specifications table 6.42 SYM53C710 bus mode 2 mux mode read timings symbol parameter min max units t 1 bclk high to address driven 6 22 ns t 2 bclk high to address high-z ? 23 ns t 3 read data setup to bclk high 5 ? ns t 4 read data hold from bclk high 6 ? ns table 6.43 SYM53C710-1 bus mode 2 mux mode read timings symbol parameter min max units t 1 bclk high to address driven 6 18 ns t 2 bclk high to address high-z ? 18 ns t 3 read data setup to bclk high 5 ? ns t 4 read data hold from bclk high 6 ? ns
bus mode 2 mux mode operation 6-65 figure 6.25 mux mode read cycle (noncache line burst) figure 6.26 mux mode read cycle (cache line burst) ta / read data (driven by memory) (driven by memory) ts/ (driven by SYM53C710) master/ (driven by SYM53C710) bg/ (driven by cpu) grant own start ack start ack release bclk t 4 t 3 address (driven by SYM53C710) #1 #2 t 2 t 1 valid #1 valid #2 ta / read data (driven by memory) (driven by memory) ts/ (driven by SYM53C710) master/ (driven by SYM53C710) bg/ (driven by cpu) grant own start ack ack ack ack bclk t 4 t 3 address (driven by SYM53C710) #1 t 2 t 1 valid #1 #2 #3 #4 release
6-66 electrical specifications 6.12.2 mux mode write cycle (cache line and noncache line burst) mux mode write sequence 1. the SYM53C710 has attained bus mastership. 2. the SYM53C710 asserts the read/write, snoop control, function control, and transfer type lines. 3a. the SYM53C710 asserts transfer in progress and transfer start. 3b. the SYM53C710 asserts transfer start, address, size lines, and floats the data lines. 4. the SYM53C710 deasserts transfer start, floats the address bus, and asserts the data bus. 5. the SYM53C710 waits for transfer acknowledge, transfer burst inhibit, and transfer error acknowledge. ? if transfer burst inhibit is not asserted, attempt cache bursting. ? if transfer error acknowledge and transfer acknowledge are asserted, attempt a retry. ? if transfer error acknowledge is asserted and transfer acknowledge is not asserted, a bus fault condition will be generated. ? if transfer acknowledge is asserted, transfer error acknowledge is not asserted, and the SYM53C710 requires more cycles, return to step 4. 6. the SYM53C710 deasserts the control and data lines. 7. upon acknowledgment of the last bus cycle, the SYM53C710 deasserts master and bus grant acknowledge. note: this mode of operation expects d[31:0] to be physically tied to a[31:0], respectively.
bus mode 2 mux mode operation 6-67 table 6.44 SYM53C710 bus mode 2 mux mode write timings symbol parameter min max units t 1 bclk high to old data driven ? 34 ns t 2 bclk high to address driven 6 22 ns t 3 bclk high to new data driven 8 24 ns t 4 high-z to driven switching time 1 ? ns t 5 bclk high to next data ? 19 ns table 6.45 SYM53C710-1 bus mode 2 mux mode write timings symbol parameter min max units t 1 bclk high to old data driven ? 28 ns t 2 bclk high to address driven 6 18 ns t 3 bclk high to new data driven 8 18 ns t 4 high-z to driven switching time 1 ? ns t 5 bclk high to next data ? 16 ns
6-68 electrical specifications figure 6.27 mux mode write cycle (noncache line burst) figure 6.28 mux mode write cycle (cache line burst) ta / write data (driven by SYM53C710) (driven by memory) ts/ (driven by SYM53C710) master/ (driven by SYM53C710) bg/ (driven by cpu) grant own start ack start ack release bclk t 4 address (driven by SYM53C710) t 2 valid #1 data #1 data #2 old data t 3 t 4 valid #2 t 1 ta / write data (driven by SYM53C710) (driven by memory) ts/ (driven by SYM53C710) master/ (driven by SYM53C710) bg/ (driven by cpu) grant own start ack ack ack release bclk address (driven by SYM53C710) t 2 valid #1 old data data #1 data #2 data #3 data #4 t 3 t 4 t 4 t 5 t 1
bus mode 2 mux mode operation 6-69 figure 6.29 initiator asynchronous send figure 6.30 initiator asynchronous receive valid n valid n + 1 n+1 n+1 n n t 1 t 2 t 3 t 4 req/ ack/ sd[7:0]/, sdp/ table 6.46 initiator asynchronous send timings symbol parameter min max units t 1 ack/ asserted from req/ asserted 10 ? ns t 2 ack/ deasserted from req/ deasserted 10 ? ns t 3 data setup to ack/ asserted 55 ? ns t 4 data hold from req/ deasserted 20 ? ns valid n valid n + 1 n+1 n+1 n n t 1 t 2 t 3 t 4 req/ ack/ sd[7:0]/, sdp/ table 6.47 initiator asynchronous receive timings symbol parameter min max units t 1 ack/ asserted from req/ asserted 10 ? ns t 2 ack/ deasserted from req/ deasserted 10 ? ns t 3 data setup to req/ asserted 0 ? ns t 4 data hold from ack/ deasserted 0 ? ns
6-70 electrical specifications figure 6.31 target asynchronous send figure 6.32 target asynchronous receive valid n valid n + 1 n+1 n+1 n n t 1 t 2 t 3 t 4 req/ ack/ sd[7:0]/, sdp/ table 6.48 target asynchronous send timings symbol parameter min max units t 1 req/ deasserted from ack/ asserted 10 ? ns t 2 req/ asserted from ack/ deasserted 10 ? ns t 3 data setup to req/ asserted 55 ? ns t 4 data hold from ack/ asserted 20 ? ns valid n valid n + 1 n+1 n+1 n n t 1 t 2 t 3 t 4 req/ ack/ sd[7:0]/, sdp/ table 6.49 target asynchronous receive timings symbol parameter min max units t 1 req/ deasserted from ack/ asserted 10 ? ns t 2 req/ asserted from ack/ deasserted 10 ? ns t 3 data setup to ack/ asserted 0 ? ns t 4 data hold from req/ deasserted 0 ? ns
bus mode 2 mux mode operation 6-71 figure 6.33 initiator and target synchronous transfers valid n valid n + 1 n+1 n t 1 t 2 t 3 t 4 req/ send data receive data sdp/ or ack/ sd[7:0]/, sdp/ sd[7:0]/, t 5 t 6 valid n + 1 valid n table 6.50 scsi-1 transfers (se 5.0 mbytes/s) symbol parameter min max units t 1 send req/ or ack/ assertion pulse width 90 ? ns t 2 send req/ or ack/ deassertion pulse width 90 ? ns t 1 receive req/ or ack/ assertion pulse width 90 ? ns t 2 receive req/ or ack/ deassertion pulse width 90 ? ns t 3 send data setup to req/ or ack/ asserted 55 ? ns t 4 send data hold from req/ or ack/ asserted 100 ? ns t 5 receive data setup to req/ or ack/ asserted 0 ? ns t 6 receive data hold from req/ or ack/ asserted 45 ? ns
6-72 electrical specifications table 6.51 scsi-1 transfers (differential, 4.17 mbytes/s) symbol parameter min max units t 1 send req/ or ack/ assertion pulse width 95 ? ns t 2 send req/ or ack/ deassertion pulse width 95 ? ns t 1 receive req/ or ack/ assertion pulse width 84 ? ns t 2 receive req/ or ack/ deassertion pulse width 84 ? ns t 3 send data setup to req/ or ack/ asserted 63 ? ns t 4 send data hold from req/ or ack/ asserted 110 ? ns t 5 receive data setup to req/ or ack/ asserted 0 ? ns t 6 receive data hold from req/ or ack/ asserted 45 ? ns table 6.52 scsi-2 fast transfers (10.0 mbytes/s, 40 mhz clock) symbol parameter min max units t 1 send req/ or ack/ assertion pulse width 35 ? ns t 2 send req/ or ack/ deassertion pulse width 35 ? ns t 1 receive req/ or ack/ assertion pulse width 24 ? ns t 2 receive req/ or ack/ deassertion pulse width 24 ? ns t 3 send data setup to req/ or ack/ asserted 33 ? ns t 4 send data hold from req/ or ack/ asserted 45 ? ns t 5 receive data setup to req/ or ack/ asserted 0 ? ns t 6 receive data hold from req/ or ack/ asserted 10 ? ns
bus mode 2 mux mode operation 6-73 table 6.53 scsi-2 fast transfers (10.0 mbytes/s, 50 mhz clock) 1 1. for fast scsi, the enable active negation bit ( chip test zero (ctest0) , bit 4) should be set. transfer period bits (bits [6:4] in scsi transfer (sxfer) register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) )isset. symbol parameter min max units t 1 send req/ or ack/ assertion pulse width 35 ? ns t 2 send req/ or ack/ deassertion pulse width 35 ? ns t 1 receive req/ or ack/ assertion pulse width 24 ? ns t 2 receive req/ or ack/ deassertion pulse width 24 ? ns t 3 send data setup to req/ or ack/ asserted 33 ? ns t 4 send data hold from req/ or ack/ asserted 40 2 2. analysis of system configuration is recommended due to reduced driver skew margin in differential systems. ?ns t 5 receive data setup to req/ or ack/ asserted 0 ? ns t 6 receive data hold from req/ or ack/ asserted 10 ? ns
6-74 electrical specifications
symbios SYM53C710 scsi i/o processor a-1 appendix a register summary table a.1 SYM53C710 register map register name big endian/little endian read/write page scsi control zero (scntl0) 0x00 (0x03) read/write 4-3 scsi control one (scntl1) 0x01 (0x02) read/write 4-6 scsi destination id (sdid) 0x02 (0x01) read/write 4-8 scsi interrupt enable (sien) 0x03 (0x00) read/write 4-9 scsi chip id (scid) 0x04 (0x07) read/write 4-10 scsi transfer (sxfer) 0x05 (0x06) read/write 4-10 scsi output data latch (sodl) 0x06 (0x05) read/write 4-14 scsi output control latch (socl) 0x07 (0x04) read/write 4-14 scsi first byte received (sfbr) 1 0x08 (0x0b) read/write 4-15 scsi input data latch (sidl) 0x09 (0x0a) read only 4-16 scsi bus data lines (sbdl) 0x0a read only 4-17 scsi bus control lines (sbcl) 0x0b (0x08) read/write 4-17 dma status (dstat) 0x0c (0x0f) read only 4-18 scsi status zero (sstat0) 0x0d (0x0e) read only 4-20 scsi status one (sstat1) 0x0e (0x0d) read only 4-23 scsi status two (sstat2) 0x0f (0x0c) read only 4-25 data structure address (dsa) 0x10?0x13 (0x10?0x13) read/write 4-26 chip test zero (ctest0) 0x14 (0x17) read/write 4-26 chip test one (ctest1) 0x15 (0x16) read only 4-28
a-2 register summary 1. write restrictions apply; refer to register description. chip test two (ctest2) 0x16 (0x15) read only 4-28 chip test three (ctest3) 0x17 (0x14) read only 4-30 chip test four (ctest4) 0x18 (0x1b) read/write 4-30 chip test five (ctest5) 0x19 (0x1a) read/write 4-32 chip test six (ctest6) 0x1a (0x19) read/write 4-34 chip test seven (ctest7) 0x1b (0x18) read/write 4-35 temporary stack (temp) 0x1c (0x1c?0x1f) read/write 4-37 dma fifo (dfifo) 0x20 (0x23) read/write 4-37 interrupt status (istat) 0x21 (0x22) read/write 4-38 chip test eight (ctest8) 0x22 (0x21) read/write 4-41 longitudinal parity (lcrc) 0x23 (0x20) read/write 4-43 dma byte counter (dbc) 0x24?0x26 (0x25?0x27) read/write 4-44 dma command (dcmd) 0x27 (0x24) read/write 4-44 dma next data address (dnad) 0x28?0x2b (0x28?0x2b) read/write 4-45 dma scripts pointer (dsp) 0x2c?0x2f (0x2c?0x2f) read/write 4-45 dma scripts pointer save (dsps) 0x30?0x33 (0x30?0x33) read/write 4-46 scratch (scratch) 0x34?0x37 (0x34?0x37) read/write 4-46 dma mode (dmode) 0x38 (0x3b) read/write 4-47 dma interrupt enable (dien) 0x39 (0x3a) read/write 4-49 dma watchdog timer (dwt) 0x3a (0x39) read/write 4-50 dma control (dcntl) 0x3b (0x38) read/write 4-51 adder sum output (adder) 0x3c?0x3f (0x3c?0x3f) read only 4-53 table a.1 SYM53C710 register map (cont.) register name big endian/little endian read/write page
symbios SYM53C710 scsi i/o processor b-1 appendix b register and bit differences between the SYM53C710 and sym53c700 the SYM53C710 can execute all sym53c700 scripts without recompilation. however, because there are new registers and bits, and some registers and bits have been relocated or deleted, firmware drivers need to be modified. ta bl e b . 1 through ta b l e b . 3 summarize the differences between the sym53c700 and SYM53C710 register sets. the byte addresses are referenced using little endian byte orientation.
b-2 register and bit differences between the SYM53C710 and sym53c700 table b.1 new registers and bits item sym53c700 SYM53C710 synchronous scsi clock control bits n/a sbcl, bits [1:0] bus fault bit n/a dstat, bit 5 data structure address register n/a dsa signal process test & reset bit n/a ctest2, bit 6 mux mode bit n/a ctest4, bit 7 cache burst disable bit n/a ctest7, bit 7 snoop control bits [1:0] n/a ctest7, bits [6:5] transfer type one bit n/a ctest7, bit 1 byte offset six bit n/a dfifo, bit 6 signal process set bit n/a istat, bit 5 ctest8 register n/a ctest8 fetch/ pin control bit n/a ctest8, bit 1 snoop mode bit n/a ctest8, bit 0 lcrc register n/a lcrc scratch register n/a scratch function code bits [2:1] n/a dmode, bits [5:4] program/data function code 0 control bit n/a dmode, bit 3 upso-tt0/bit n/a dmode, bit 1 bust fault interrupt enable bit n/a dien, bit 5 enable acknowledge control bit n/a dcntl, bit 5 fast arbitration mode bit n/a dcntl, bit 1 sym53c700 compatibility bit n/a dcntl, bit 0 adder output register n/a adder filter delay select bit n/a ctest0, bit 2 halt scsi clock bit n/a ctest0, bit 3 enable active deassertion bit n/a ctest0, bit 4 generate receive parity bit n/a ctest0, bit 5 byte-to-byte disable bit n/a ctest0, bit 6
b-3 table b.2 deleted bits item sym53c700 SYM53C710 dc/pin control bit ctest7, bit 1 n/a dsps and dsp empty bit istat, bit 2 n/a 16-bit dma, 286 mode bits dmode, bits [5:4] n/a i/o memory mapped dma bit dmode, bit 3 n/a pipeline mode bit dmode, bit 1 n/a 16-bit scsi scripts mode bit dcntl, bit 5 n/a real target mode bit ctest0, bit 1 n/a start scsi send scntl, bit 1 n/a start scsi receive scntl, bit 0 n/a table b.3 moved registers and bits item sym53c700 SYM53C710 flush fifo bit dfifo, bit 7 ctest8, bit 3 clear fifo bit dfifo, bit 6 ctest8, bit 2 software reset bit dcntl, bit 0 istat, bit 6 chip revision level bits ctest7, bits [7:4] ctest8, bits [7:4] dmode register address 34h address 38h
b-4 register and bit differences between the SYM53C710 and sym53c700
symbios SYM53C710 scsi i/o processor c-1 appendix c mechanical drawing figure c.1 160-pin pqfp (pz) mechanical drawing (sheet 1 of 2) important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pz.
c-2 mechanical drawing figure c.1 160-pin pqfp (pz) mechanical drawing (sheet 2 of 2) important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pz.
symbios SYM53C710 scsi i/o processor d-1 appendix d setting data transfer rates this appendix contains the following sections: ? section d.1, ?setting the sym53c700-66 transfer rate? ? section d.2, ?sym53c7xx, sym53c8xx to 75lbc976/76a differential interface? d.1 setting the sym53c700-66 transfer rate this appendix explains how to get the proper data transfer speed on the scsi bus when using the sym53c700-66 scsi i/o processor chip. data transfer rates are controlled by the configuration of the following bits. register 0x0b scsi bus control line (sbcl) - bits 1 (sscf1) and 0 (sscf0) ? sscf[1:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider must not exceed 50 mhz. register 0x3b dma control (dcntl) - bits 7 (cf1) and 6(cf0)? cf[1:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the table. the output from this divider must not exceed 25 mhz. register 0x05 scsi transfer (sxfer) - bits 6 (tp2), 5 (tp1) and 4 (tp0) ? tp[2:0] determines the scsi synchronous transfer period when sending synchronous scsi data in either initiator or target mode. these bits control the programmable dividers in the chip. on the following page are tables of these bits and the division factors they produce. figure d.1 shows how the chip uses the divisors.
d-2 setting data transfer rates figure d.1 divisor usage sclk sscf divider cf divider synchronous scsi logic asynchronous scsi logic sscf1 sscf0 sscf divisor 0 0 set by dcntl 011.0 101.5 112.0 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 cf1 cf0 cf divisor sclk (mhz) 0 0 2.0 37.51?50.00 0 1 1.5 25.01?37.50 1 0 1.0 16.67?25.00 1 1 3.0 50.01?66.67 example: sclk = 40 mhz, scsi transfer rate = 10 mbytes/s sscf = 1, cf = 0, xferp = 4 (tp = 0) this point must not exceed 50 mhz this point must not exceed 25 mhz (40 mhz / 1 = 40 mhz synchronous logic speed) (40 mhz / 2 = 20 mhz asynchronous logic speed) scsi synchronous logic speed / xferp = scsi synchronous rate (40 mhz / 4 = 10 mhz = 10 mbytes/s)
sym53c7xx, sym53c8xx to 75lbc976/76a differential interface d-3 d.2 sym53c7xx, sym53c8xx to 75lbc976/76a differential interface following is a suggested interface between the sym53c700, sym53c700-66, SYM53C710, sym53c720, or sym53c820 scsi i/o processors (siop) and the texas instruments 75lbc976 differential transceiver. this appendix does not apply to the sym53c810, which has a single-ended (se) interface only. the 75lbc976 is capable of 10 mbytes/s transfers and contains nine differential transceivers in one package, which reduces the board space required to implement a differential scsi interface. the purpose of this appendix is to guide people in their own designs. the designer should perform a thorough design analysis before implementing this interface. d.2.1 differential mode the siop must be placed in differential mode by setting the dif bit, bit 5 of the stest2 register (0x4e) in the sym53c720 and sym53c820, or bit 0 of the ctest7 register (0x1b) in the sym53c700, sym53c700- 66, and SYM53C710. setting this bit 3-states the bsy/, sel/, and rst/ pads so they can be used as pure input pins. in addition to the standard scsi lines, the following signals are used during differential operation by the siop in all bus modes: signal function bsydir, seldir, rstdir active high signals used to enable 75lbc976 differential drivers as outputs for scsi signals bsy/, sel/, and rst/ respectively sdir[15:0], sdirp[1:0] active high signals used to control direction of 75lbc976 differential drivers for scsi data and parity lines, respectively igs active high signal used to control direction of 75lbc976 differential driver for initiator group signals atn/ and ack/ tgs active high signal used to control direction of 75lbc976 differential drivers for target group signals msg/, c/d/, i/o/, and req/ diffsens input to siop used to detect the presence of a se device on a differential system. if a logical zero is detected on this pin, then it is assumed that a se device is on the bus and all scsi outputs will be 3-stated to avoid damage to the transceiver
d-4 setting data transfer rates d.2.2 ti 75lbc976 architecture the 75lbc976 is made up of nine differential transceiver channels. each of these channels has a direction control pin and bidirectional data pin. the direction control pin, labeled nde/re/ (where n is a value from 1 through 9), controls the direction of the transceiver. pulling the signal high enables the channel as an output to the scsi bus, and low enables the channel as an input from the scsi bus. these direction control pins will be connected to the dir, igs, and tgs pins of the symbios siop. the bidirectional data pins, labeled na (n is a value from 1 through 9), are configured as inputs or outputs depending upon the state of their respective direction control (nde/re/) pins. when the direction control pin is high, the data line is configured as an input; when the direction control pin is low, the line is configured as an output. these data lines are connected to the symbios siop?s scsi data and control pins. the na and nde/re/ pins are the only direct contact with the transceiver. there are no separate pins for the input and output of the channel, nor are there separate input and output enables. the signals from the inputs and outputs of the transceiver are tied together internally to form the bidirectional data pin (na). this is also true of the enables for the input and output of the transceiver channel. these two enables, one active high and the other active low, are tied together internally to form the direction control pin (nde/re/). an example transceiver channel is shown in figure d.2 . there are five other control pins on the 75lbc976 labeled cde0, cde1, cde2, bsr, and cre/. all of these lines are grounded in the interface except for cde0. this pin controls the functionality of all the channels on the transceiver. when this pin is high, the channels are configured as fully functional bidirectional transceivers. when it is low, they are configured as input only transceivers. the cde0 pin is connected to the diffsens scsi signal, to protect the transceiver if a se device is plugged onto the scsi bus.
sym53c7xx, sym53c8xx to 75lbc976/76a differential interface d-5 figure d.2 ti 75lbc976 differential transceiver d.2.3 interface to interface the symbios siop to the 75lbc976, connect the dir pins, as well as igs and tgs, of the siop directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the 75lbc976. the scsi bidirectional control and data pins (sd[7:0]/, sdp0/, req/, ack/, msg/, i_o/, c_d/, and atn/) of the symbios siop connect to the bidirectional data pins (na) of the 75lbc976 with a pull-up resistor. the three remaining pins, sel/, bsy/, and rst/ are connected to the 75lbc976 with a pull-down resistor. the pull-down resistors are required when the data pins (na) of the 75lbc976 are configured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the siop pins (sel/, bsy/, and rst/) and the 75lbc976 data pins. because the sel/, bsy/, and rst/ pins on the symbios siop are inputs only, this configuration allows for the sel/, bsy/ and rst/ scsi signals to be asserted on the scsi bus. the interfaceinshownin figure d.3 . d.2.4 pull-up resistor value the recommended value of the pull-up resistor on the req/, ack/, msg/, c/d/, i/o/, atn/, sd[0:7]/, and sdp0/ lines is 680 ? = when the active negation portion of symbios tolerant technology is not enabled. when tolerant is enabled, the recommended resistor value on the req/, ack/, sd[7:0]/, and sdp0/ signals is 1.5 k ?. the electrical characteristics of these pins change when tolerant is enabled, permitting a higher resistor value. a dr/re b+ b ?
d-6 setting data transfer rates d.2.5 8-bit/16-bit scsi and the differential interface the interface described in this appendix is for an 8-bit scsi bus. for a 16-bit bus (wide scsi, supported on sym53c720 and sym53c820 only) another 75lbc976 should be used in the same fashion as the 75lbc976#2in figure d.3 . sd[8:15]/, sdir[8:15], sdp1/ and sdirp1 should be connected to the third 75lbc976. note: in an 8-bit scsi bus, the sd[15:8] pins on the symbios siopshouldbepulledupwitha1k ? resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left floating.
sym53c7xx, sym53c8xx to 75lbc976/76a differential interface d-7 figure d.3 symbios siop to 75lbc976 differential interface symbios siop seldir bsydir rstdir sel/ bsy/ rst/ req/ ack / msg/ c/d/ i/o/ at n / tgs igs sd[8:15] sdirp0/ sdir7/ sdir6/ sdir5/ sdir4/ sdir3/ sdir2/ sdir1/ sdir0/ sdp/ sd7/ sd6/ sd5/ sd4/ sd3/ sd2/ sd1/ sd0/ diffsens 680 ? vdd vdd vdd vdd vdd 75lbc976 #1 cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re sel/ seldir bsydir rstdir req/ bsy/ rst/ ack / msg / c_d / i_o / at n / vdd 1k ? diffsens schottky diode (pin 21) ? sel scsi bus +sel ? bsy +bsy ? rst (42) +rst ? req +req ? ack +ack ? msg +msg ? c/d +c/d ? i/o +i/o ? at n +atn 1b+ 1b ? 2b+ 2b ? 3b+ 3b ? 4b+ 4b ? 5b+ 5b ? 6b+ 6b ? 7b+ 7b ? 8b+ 8b ? 9b+ 9b ? (41) (34) (33) (38) (37) (46) (45) (36) (35) (40) (39) (46) (45) (36) (35) (40) (39) 75lbc976 #2 cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re ? db0 +db0 ? db1 +db1 ? db2 (4) +db2 ? db3 +db3 ? db4 +db4 ? db5 +db5 ? db6 +db6 ? db7 +db7 ? dbp +dbp 1b+ 1b ? 2b+ 2b ? 3b+ 3b ? 4b+ 4b ? 5b+ 5b ? 6b+ 6b ? 7b+ 7b ? 8b+ 8b ? 9b+ 9b ? (3) (6) (5) (8) (7) (10) (9) (12) (11) (14) (13) (16) (15) (18) (17) (20) (19) diffsens diffsens sdir0 sdir1 sdir2 sdir3 sdir4 sdir5 sdir6 sdir7 sdirp sd0/ sd1/ sd2 / sd3 / sd4/ sd5/ sd6/ sd7/ sdp/ 1k ? (sym53c720/ sym53c820 only) 680 ? 680 ? 680 ? 680 ?
d-8 setting data transfer rates
symbios SYM53C710 scsi i/o processor ix-1 index symbols (abrt) 4-39 (adck) 4-32 (bbck) 4-32 (bf) 4-49 (bl[1:0]) 4-47 (com) 4-53 (ctest0) 4-26 (ctest1) 4-28 (ctest4) 4-30 (ctest5) 4-32 (ctest6) 4-34 (dack) 4-30 , 4-34 (dbc) 4-44 (dcmd) 4-44 (dcntl) 4-51 (ddir) 4-33 (dfifo) 4-37 (dien) 4-49 (dip) 4-41 (dmode) 4-47 (dnad) 4-45 (dreq) 4-29 , 4-33 (dsa) 4-26 (dsp) 4-45 (dsps) 4-46 (flf) 4-42 (fm) 4-42 (hsc) 4-27 (iid) 4-49 (istat) 4-38 (masr) 4-33 (scratch) 4-46 (sigp) 4-28 , 4-39 (sir) 4-19 , 4-49 (srst) 4-39 (ssi) 4-49 (ssm) 4-51 (std) 4-52 (teop) 4-29 (v[3:0]) 4-41 a abort operation (abrt) 4-39 , 4-49 active termination 2-27 arbitration in progress bit 4-24 arbitration mode bits 4-3 assert atn/ on parity error bit 4-5 assert even scsi parity bit 4-8 assert scsi data bus bit 4-7 assert scsi rst/ bit 4-7 b block move instructions sfbr register 4-15 burst length (bl[1:0]) 4-47 bus fault (bf) 4-49 bus mode 1 timings arbitration 6-21 slave cycle 6-14 bus mode 2 timings master cycle 6-53 c cache burst disable bit 4-35 chip revision level (v[3:0]) 4-41 test five (ctest5) 4-32 test four (ctest4) 4-30 test one (ctest1) 4-28 test six (ctest6) 4-34 test two (ctest2) 4-28 test zero (ctest0) 4-26 chip testing 1-4 clear instruction 5-13 , 5-15 clock address incrementor (adck) 4-32 byte counter (bbck) 4-32 connected bit 4-7 d data acknowledge status (dack) 4-30 , 4-34 request status (dreq) 4-29 , 4-33 structure address (dsa) 4-26 differential interface 2-26 direct addressing 5-16 disconnect instruction 5-12 dma byte counter (dbc) 4-44 command (dcmd) 4-44 control (dcntl) 4-51 direction (ddir) 4-33 fifo (dfifo) 4-37
ix-2 index interrupt enable (dien) 4-49 interrupt pending (dip) 4-41 mode (dmode) 4-47 next address (dnad) 4-45 scripts pointer (dsp) 4-45 pointer save (dsps) 4-46 dma core 2-2 e enable parity checking bit 4-5 enable parity generation/pass-through bit 4-5 extra clock cycle of data setup bit 4-6 f fetch pin mode (fm) 4-42 flush dma fifo (flf) 4-42 functional description dma core 2-2 scripts processor 2-2 scsi core 2-1 h halt scsi clock (hsc) 4-27 high impedance mode bit 4-31 host bus multiplex mode bit 4-30 host interface misaligned transfers 2-11 i i/o instructions disconnect 5-12 relative addressing 5-15 table indirect addressing 5-15 illegal instruction detected (iid) 4-49 initiator mode 5-13 instructions format 5-2 interrupt status (istat) 4-38 interrupt handling 2-21 to 2-26 registers 2-21 sample interrupt service routine 2-25 stacked interrupts 2-24 interrupt instruction 5-25 interrupts 2-21 to 2-26 hardware vs. polling 2-21 registers 2-21 sample interrupt service routine 2-25 stacked interrupts 2-24 j jump instruction 5-23 l lost arbitration bit 4-24 m master control for set or reset pulses (masr) 4-33 memory move instructions read/write system memory 5-31 misaligned transfers 2-11 multithreaded operation 2-27 p parity aap bit 4-5 epc bit 4-5 epg bit 4-5 polling and hardware interrupts 2-21 r read-modify-write operations sfbr register 4-16 register bits aap 4-5 adb 4-7 aesp 4-8 aip 4-24 arbitration in progress 4-24 arbitration mode bits 4-3 assert atn/ on parity error 4-5 assert even scsi parity 4-8 assert scsi data bus 4-7 assert scsi rst/ 4-7 cache burst disable 4-35 cdis 4-35 con 4-7 connected 4-7 enable parity checking 4-5 enable parity generation/pass-through 4-5 epc 4-5 epg 4-5 exc 4-6 extra clock cycle of data setup 4-6 high impedance mode 4-31 host bus multiplex mode 4-30 loa 4-24 lost arbitration 4-24 mux 4-30 rst 4-7 sc[1:0] 4-35 scsi c_d/ signal 4-25 scsi i_o/ signal 4-25 scsi msg/ signal 4-25 scsi rst/ signal 4-24 select with atn on start sequence 4-5 snoop control 4-35 start sequence 4-4 target mode 4-6 trg 4-6 watn 4-5 woa 4-24 won arbitration 4-24 zmod 4-31 register map a-1 registers sbcl 4-17
index ix-3 scid 4-10 scntl0 4-3 scntl1 4-6 scsi bus control lines 4-17 scsi chip id 4-10 scsi control one 4-6 scsi control zero 4-3 scsi first byte received 4-15 scsi status one 4-23 scsi status two 4-25 scsi status zero 4-20 sfbr 4-15 sodr 4-23 sstat0 4-20 sstat1 4-23 sstat2 4-25 relative addressing 5-16 i/o instructions 5-15 reliability 1-4 reselect instruction 5-11 return instruction 5-24 s sample interrupt service routine 2-25 scid register 4-10 scntl1 register 4-6 scratch register (scratch) 4-46 scripts interrupt instruction received (sir) 4-49 scripts processor 2-2 features 2-2 scsi true end of process 4-29 scsi bus control lines register 4-17 scsi bus interface 2-26 differential interface 2-26 scsi c_d/ signal bit 4-25 scsi chip id register 4-10 scsi control one register 4-6 scsi core 2-1 scsi first byte received register 4-15 scsi i_o/ signal bit 4-25 scsi interface termination 2-27 scsi msg/ signal bit 4-25 scsi rst/ signal bit 4-24 scsi status one register 4-23 scsi status two register 4-25 scsi status zero register 4-20 select with atn on start sequence bit 4-5 select/reselect during selection/reselection 2-27 set instruction 5-12 , 5-14 sfbr register 4-15 signal process (sigp) 4-28 , 4-39 single step mode (ssm) 4-51 snoop control bit 4-35 sodr register 4-23 software reset (srst) 4-39 stacked interrupts 2-24 start dma operation (std) 4-52 start sequence bit 4-4 sym53c700 compatibility (com) 4-53 SYM53C710 register map a-1 SYM53C710 testability 1-4 symbios scsi scripts 2-2 t table indirect addressing 5-16 table indirect operations i/o instructions 5-15 table relative addressing 5-17 target mode 5-11 target mode bit 4-6 , 5-7 terminator networks scsi termination 2-27 testing 1-4 transfer control instructions interrupt 5-25 jump 5-23 return 5-24 w wait reselect instruction 5-14 wait select instruction 5-12 won arbitration bit 4-24
ix-4 index
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for hab?s) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 te m p e i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 ta m p a w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tu l s a a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 springfield b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (component and hab) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. infinity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona te m p e e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plainfield r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales offices and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 ? tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales office m/s c-500 milpitas, ca 95035 ? tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 ? tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 danfield court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 ? tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 ? tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook office park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 ? tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 ? tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris ? tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich ? tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart ? tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano ? tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 ? tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 ? tel: 81.6.947.5281 fax: 81.6.947.5287
sales offices and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building ?rijder? bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista ? tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan ta i p e i lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub ? tel: 44.1344.426544 fax: 44.1344.481039 ? sales offices with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 ? tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative office room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 ? tel: 91.80.664.5530 fax: 91.80.664.9748 israel te l av i v eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan ta i p e i avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 ? sales offices with design resource centers

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